KR20090105561A - Semiconductor device and flat panel display device having same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a thin film transistor and a capacitor, and to a flat panel display device including the same. An insulating layer formed over the lower electrode, the gate electrode and the lower electrode formed on the substrate of the electrode and the second region, an oxide semiconductor formed over the insulating layer over the gate electrode, and including a channel region, a source region, and a drain region. A passivation layer formed over the active layer and the insulating layer on the lower electrode, the upper electrode including the active layer and the upper electrode formed of an oxide semiconductor and patterned to expose the source and drain regions and the upper electrode, and the source and drain regions. And a source electrode and a drain electrode in contact with each other.

Description

Semiconductor device and flat panel display device having same {Semiconductor device and flat panel display device having the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a thin film transistor and a capacitor, and a flat panel display device including the same. More specifically, a thin film transistor and an MIS (Metal-Insulator-) having an oxide semiconductor as an active layer. A semiconductor device including a capacitor having a semiconductor structure and a flat panel display device having the same.

In general, the thin film transistor includes an active layer providing a channel region, a source region and a drain region, and a gate electrode formed on the channel region and electrically insulated from the active layer by a gate insulating layer.

The active layer of the thin film transistor formed as described above is usually formed of a semiconductor material such as amorphous silicon or poly-silicon. When the active layer is formed of amorphous silicon, it is operated at high speed due to low mobility. It is difficult to implement the driving circuit, and when formed of polysilicon, there is a problem in that the mobility is high but the threshold voltage is uneven so that a separate compensation circuit must be added.

In addition, the conventional thin film transistor manufacturing method using low temperature poly-silicon (LTPS) has a problem that it is difficult to apply to a large-area substrate because expensive processes such as laser heat treatment and the like is difficult to control characteristics. .

In order to solve this problem, researches using an oxide semiconductor as an active layer have recently been conducted.

Japanese Laid-Open Patent Publication No. 2004-273614 discloses a thin film transistor using an oxide semiconductor containing zinc oxide (ZnO) or zinc oxide (ZnO) as a main component.

Oxide semiconductors containing zinc oxide (ZnO) as the main component are evaluated as amorphous and stable materials. By using such oxide semiconductors as active layers, thin film transistors can be manufactured by conventional low-temperature polysilicon (LTPS) processes, and 300 ° C. The process becomes possible even at the following low temperatures.

However, in order to apply an oxide semiconductor containing zinc oxide (ZnO) as a main component to devices, it is necessary to develop processes and improve characteristics to satisfy electrical characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a flat panel display device having the same, which can prevent the deterioration of electrical characteristics due to the damage of the oxide semiconductor layer.

Another object of the present invention is to provide a semiconductor device capable of securing the capacitance of a capacitor without increasing its area and a flat panel display device having the same.

In accordance with an aspect of the present invention, a semiconductor device includes: a substrate including a first region and a second region; A gate electrode formed on the substrate in the first region and a lower electrode formed on the substrate in the second region; An insulating layer formed on the top including the gate electrode and the lower electrode; An upper layer formed of an oxide semiconductor on the insulating layer above the gate electrode, the active layer including a channel region, a source region and a drain region, and an upper electrode formed of the oxide semiconductor on the insulating layer above the lower electrode; A passivation layer formed over the active layer and the upper electrode and patterned to expose the source and drain regions and the upper electrode; And a source electrode and a drain electrode in contact with the source region and the drain region.

According to another aspect of the present invention, a method of manufacturing a semiconductor device includes: preparing a substrate including a first region and a second region; Forming a gate electrode on the substrate in the first region, and forming a lower electrode on the substrate in the second region; Forming an insulating layer on the top including the gate electrode and the bottom electrode; After forming an oxide semiconductor layer on the insulating layer and patterning, an active layer including a channel region, a source region and a drain region is formed on the insulating layer on the gate electrode, an upper electrode on the insulating layer on the lower electrode Allowing it to be formed; Forming a passivation layer on the active layer and the upper electrode and patterning the protective layer to expose the source and drain regions and the upper electrode; And forming a source electrode and a drain electrode to be in contact with the source region and the drain region.

The present invention forms the active layer of the thin film transistor as an oxide semiconductor layer, so that the oxide semiconductor layer in the channel region is protected by a protective film. By allowing the passivation layer to act as an etch stop layer, degradation of the electrical properties of the active layer due to damage occurring in subsequent processes may be prevented.

The present invention also forms the upper electrode of the capacitor as an oxide semiconductor layer. Damage to the insulating layer (dielectric) can be prevented by the oxide semiconductor layer, and a predetermined level or more of capacitance can be secured in a predetermined area. When the semiconductor device of the present invention is applied to a display device, the electrical characteristics are improved, and the resolution can be increased by minimizing the area occupied by the capacitor to improve the aperture ratio.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. no.

1 is a cross-sectional view illustrating a semiconductor device according to the present invention.

The substrate 10 made of an insulator includes a thin film transistor forming region T and a capacitor forming region C, and a buffer layer 12 on the substrate 10 of the thin film transistor forming region T and the capacitor forming region C. Is formed.

The gate electrode 14a is formed on the buffer layer 12 of the thin film transistor forming region T, and the lower electrode 14b is formed on the buffer layer 12 of the capacitor forming region C, and the gate electrode 14a and the lower part of the thin film transistor forming region T are formed. An insulating layer 16 is formed on the upper surface including the electrode 14b. The insulating layer 16 is used as the gate insulating layer of the thin film transistor and the dielectric of the capacitor.

An active layer 18a made of an oxide semiconductor and including a channel region, a source region and a drain region is formed on the insulating layer 16 on the gate electrode 14a, and on the insulating layer 16 on the lower electrode 14b. An upper electrode 18b made of an oxide semiconductor is formed.

On the upper surface including the active layer 18a and the upper electrode 18b, a passivation layer 20 is formed to expose the active layer 18a and the upper electrode 18b of the source region and the drain region, and the passivation layer 20 is formed on the passivation layer 20. The source and drain electrodes 22a and 22b are formed to be connected to the active layers 18a of the source and drain regions.

In the semiconductor device of the present invention, the thin film transistor has an active layer 18a formed of an oxide semiconductor, and the capacitor has a MIS of a lower electrode 14a made of metal, an insulating layer 16 and an upper electrode 18b made of an oxide semiconductor. (Metal-Insulator-Semiconductor) structure.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention, and the semiconductor device of the present invention will be described in more detail through the manufacturing process.

Referring to FIG. 2A, an insulating substrate 10 having a thin film transistor formation region T and a capacitor formation region C is prepared. First, the buffer layer 12 is formed on the substrate 10 of the thin film transistor forming region T and the capacitor forming region C. Referring to FIG. A metal layer is formed on the buffer layer 12 using Mo, MoW, Al, and the like, and is patterned to form a gate electrode 14a on the buffer layer 12 of the thin film transistor forming region T. The buffer layer of the capacitor forming region C is formed. The lower electrode 14b is formed on the 12. Thereafter, the insulating layer 16 is formed on the upper surface including the gate electrode 14a and the lower electrode 14b. The insulating layer 16 may be formed of silicon oxide (SiOx) or silicon nitride (SiNx). However, the insulating layer 16 may be formed of silicon nitride having better interfacial properties with the oxide semiconductor.

Referring to FIG. 2B, an oxide semiconductor layer is formed on the insulating layer 16 of the thin film transistor forming region T and the capacitor forming region C, and then patterned to form an oxide semiconductor layer on the insulating layer 16 on the gate electrode 14a. The active layer 18a including the channel region, the source region, and the drain region is formed, and the upper electrode 18b is formed on the insulating layer 16 on the lower electrode 14a. The oxide semiconductor layer is formed of a semiconductor material mainly composed of zinc oxide (ZnO), or a semiconductor material in which zinc oxide (ZnO) is doped with indium (In), gallium (Ga), stanium (Sn), or the like. InZnO (IZO), GaInZnO (GIZO), or the like.

Referring to FIG. 2C, after the passivation layer 20 is formed on the upper surface including the active layer 18a and the upper electrode 18b, the passivation layer may be exposed to expose the active layer 18a and the upper electrode 18b of the source and drain regions. Pattern (20). The passivation layer 20 may be formed of silicon oxide, silicon nitride, or gallium oxide.

Referring to FIG. 2D, a metal layer is formed on the passivation layer 20 using Mo, MoW, Al, AlAd, AlLiLa, and the like, and is patterned to connect the source and drain electrodes 22a connected to the active layers 18a of the source and drain regions. And 22b). In this case, the patterning process for forming the source and drain electrodes 22a and 22b includes a dry etching process, but the active layer 18a of the channel region is not damaged by the passivation layer 20 during the etching process.

As described above, the present invention forms the active layer 18a of the thin film transistor as an oxide semiconductor layer. When the oxide semiconductor layer is used as the active layer 18a, the active layer 18a in the channel region may be damaged by the plasma during the etching process for forming the source and drain electrodes 22a and 22b. When the oxide semiconductor layer is damaged by the plasma, the surface lattice is broken and oxygen defects are generated. Therefore, the electrical characteristics are deteriorated due to the decrease in the resistivity caused by the increase of the concentration of the carrier. Therefore, according to the present invention, the active layer 18a in the channel region is protected by the passivation layer 20, that is, the passivation layer 20 serves as an etch stop layer, thereby preventing deterioration of electrical characteristics of the active layer 18a. do.

The present invention also forms the upper electrode 18b of the capacitor as an oxide semiconductor layer. In order to form a capacitor having a metal-insulator-metal (MIM) structure, as illustrated in FIG. 3A, when forming the passivation layer 20, the insulating layer 16 over the lower electrode 14a must be exposed. However, when the insulating layer 16 is exposed, the insulating layer 16 of the exposed portion is etched in the etching process for forming the source electrode and the drain electrodes 22a and 22b, thereby causing a defect such as deterioration in characteristic scattering. . In order to solve this problem, as shown in FIG. 3B, the dielectric of the capacitor may be formed in a double structure of the insulating layer 16 and the passivation layer 20, but in this case, the capacitor capacity is reduced by the thick dielectric. To secure a certain level of capacitance, the area of the capacitor must be increased. Therefore, in the present invention, the upper electrode 18b of the capacitor is formed together with the gate electrode 14a as an oxide semiconductor layer, thereby preventing damage of the insulating layer 16 in the etching process for forming the source and drain electrodes 22a and 22b. At the same time, a certain level of capacitance can be ensured.

The semiconductor device of the present invention can be applied to a flat panel display such as a liquid crystal display or an organic light emitting display.

4A and 4B are plan views and cross-sectional views illustrating an example of a flat panel display device having a semiconductor device according to the present invention, and will be schematically described with reference to the display panel 200 displaying an image.

Referring to FIG. 4A, the substrate 210 is defined as a pixel region 220 and a non-pixel region 230 surrounding the pixel region 220. In the substrate 210 of the pixel region 220, a plurality of organic light emitting diodes 300 connected in a matrix manner are formed between the scan line 224 and the data line 226, and the substrate of the non-pixel region 230 is formed. In operation 210, a power supply line for the operation of the scan line 224 and the data line 226 and the organic light emitting diode 300 extending from the scan line 224 and the data line 226 of the pixel region 220. (Not shown) A scan driver 234 and a data driver 236 are formed to process a signal provided from the outside through the pad 228 and to supply the scan line 224 and the data line 226.

Referring to FIG. 5, the organic light emitting display device 300 includes an anode electrode 317 and a cathode electrode 320, and an organic thin film layer 319 formed between the anode electrode 317 and the cathode electrode 320. The organic thin film layer 319 may have a structure in which a hole transport layer, an organic light emitting layer, and an electron transport layer are stacked, and further include a hole injection layer and an electron injection layer. In addition, a thin film transistor for controlling the operation of the organic light emitting device 300 and a capacitor for holding a signal are further included. The thin film transistor and the capacitor have a structure as shown in FIG. 1, and may be manufactured according to the manufacturing method of the present invention described with reference to FIGS. 2A to 2D.

That is, after forming the thin film transistor and the capacitor on the substrate 210 through the manufacturing process of Figures 2a to 2d, the planarization layer 316 is formed on the entire upper surface. The via hole is formed in the planarization layer 316 so that the source or drain electrode 22a or 22b is exposed, and then the anode electrode 317 is formed to be connected to the source or drain electrode 22a or 22b through the via hole. The pixel defining layer 318 is formed on the planarization layer 316 so that a portion of the anode electrode 317 is exposed, and the organic thin film layer 319 is formed on the exposed anode electrode 317. . The cathode electrode 320 is formed on the pixel defining layer 318 including the organic thin film layer 319.

In the manufacturing process, the scan line 224 and the pad 228 for receiving a signal from the outside may be simultaneously formed in the process of forming the gate electrode 14a, and the signal is received from the data line 226 and the outside. The pad 228 may be simultaneously formed in the process of forming the source and drain electrodes 22a and 22b.

Referring to FIG. 4B, an encapsulation substrate 400 for encapsulating the pixel region 220 is disposed on the substrate 210 on which the organic light emitting diode 300 is formed as described above, and the encapsulation substrate is formed by the encapsulant 410. 400 is bonded to the substrate 210 to complete the display panel 200.

As described above, the preferred embodiment of the present invention has been disclosed through the detailed description and the drawings. The terms are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a cross-sectional view for explaining a semiconductor device according to the present invention.

2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present invention.

3A and 3B are cross-sectional views illustrating a semiconductor device according to the present invention.

4A and 4B are a plan view and a sectional view for explaining an example of a flat panel display device having a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view for describing the organic light emitting display device of FIG. 4A. FIG.

<Explanation of symbols for the main parts of the drawings>

10, 210: substrate 12: buffer layer

14a: gate electrode 14b: lower electrode

16: insulation layer 18a: active layer

18b: upper electrode 20: protective film

22a: source electrode 22b: drain electrode

200: display panel 220: pixel area

224: scan line 226: data line

228: pad 230: non-pixel region

234: scan driver 236: data driver

300: organic electroluminescent device 316: planarization layer

317: anode electrode 318: pixel defining film

319: organic thin film layer 320: cathode electrode

400: sealing substrate 410: sealing material

Claims (11)

A substrate comprising a first region and a second region; A gate electrode formed on the substrate in the first region and a lower electrode formed on the substrate in the second region; An insulating layer formed on the top including the gate electrode and the lower electrode; An upper layer formed of an oxide semiconductor on the insulating layer above the gate electrode, the active layer including a channel region, a source region and a drain region, and an upper electrode formed of the oxide semiconductor on the insulating layer above the lower electrode; A passivation layer formed over the active layer and the upper electrode and patterned to expose the source and drain regions and the upper electrode; And And a source electrode and a drain electrode connected to the source region and the drain region. The semiconductor device of claim 1, wherein the gate electrode and the lower electrode are formed of a metal selected from the group consisting of Mo, MoW, and Al. The semiconductor device of claim 1, wherein the insulating layer is formed of silicon oxide or silicon nitride. The semiconductor device according to claim 1, wherein the oxide semiconductor contains zinc oxide (ZnO) as a main component. The semiconductor device of claim 4, wherein at least one ion of indium (In), gallium (Ga), and stanium (Sn) is doped into the oxide semiconductor. The semiconductor device of claim 1, wherein the passivation layer is formed of a material selected from the group consisting of silicon oxide, silicon nitride, and gallium oxide. The semiconductor device of claim 1, wherein the source and drain electrodes are formed of a metal selected from the group consisting of Mo, MoW, Al, AlAd, and AlLiLa. Preparing a substrate including a first region and a second region; Forming a gate electrode on the substrate in the first region, and forming a lower electrode on the substrate in the second region; Forming an insulating layer on the top including the gate electrode and the bottom electrode; After forming an oxide semiconductor layer on the insulating layer and patterning, an active layer including a channel region, a source region and a drain region is formed on the insulating layer on the gate electrode, an upper electrode on the insulating layer on the lower electrode To be formed; Forming a passivation layer on the active layer and the upper electrode and patterning the protective layer to expose the source and drain regions and the upper electrode; And Forming a source electrode and a drain electrode so as to be connected to the source region and the drain region. The method of manufacturing a semiconductor device according to claim 8, wherein the oxide semiconductor layer is formed of zinc oxide (ZnO). The method of claim 9, wherein the oxide semiconductor layer is doped with at least one of gallium (Ga), indium (In), and stanium (Sn). The flat panel display provided with the semiconductor device of any one of Claims 1-7.

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