RU176659U1 - ANALOG-DIGITAL CONVERTER - Google Patents

Abstract

The utility model relates to measuring equipment, in particular to analog-to-digital converters, and can be used in digital systems for measuring and monitoring analog quantities. The technical result that can be achieved using the proposed utility model is to expand the functionality, increase accuracy or speed, or reduce the complexity of the circuit. The expansion of functionality consists in providing the possibility of analog-to-digital conversion of not only unipolar positive, but also unipolar negative and bipolar signals. The device contains a comparison circuit, a digital-to-analog converter, a trigger, a pulse generator, a counter, a register, a read-only memory, a prediction unit, a sign-determining and negative-inverting unit, which includes an analog inverter, a comparator, and two analog keys. 1 tablet, 5 ill.

Description

The technical field to which the utility model relates.

The utility model relates to measuring equipment, in particular to analog-to-digital converters, and can be used in digital systems for measuring and monitoring analog quantities.

State of the art

Known analog-to-digital Converter sequential approximation, containing a comparison circuit, a register of sequential approximation, digital-to-analog Converter, element And, a clock ([1]. Chernov VG Input-output devices of analog information for digital data acquisition and processing systems. - M.: Mashinostroenie, 1988. - P. 85, Fig. 57. Functional diagram and timing diagrams of the ADC of sequential approximation).

The disadvantage of this device is its low speed, since it does not take into account the statistical characteristics of the signal, the time it takes to establish the voltage at the output of the digital-to-analog converter, and the values of the codes obtained in previous conversion cycles, and also that the device can be used to measure and control only unipolar analog signals (signals positive polarity).

A prototype of the claimed technical solution is an analog-to-digital converter ([2]. Patent RU 2205500, IPC Н03М 1/26).

An analog-to-digital converter (ADC) contains: a comparison circuit; digital-to-analog converter (DAC); trigger; pulse generator; counter; register; read-only memory (ROM); prediction unit, moreover: the input conversion voltage is supplied to the first input of the comparison circuit, which is the first input of the device, and the DAC output is connected to the second input of the comparison circuit, the inputs of which are connected to the register outputs, the second inputs of the prediction unit, the third inputs of the ROM and are the first outputs devices the second input of the device is connected to the first input of the register and the first input of the trigger, the output of which is the second output of the device, and in addition, connected to the first input of the prediction unit and the input of the pulse generator, the first output of which is connected to the first input of the counter, and the second output is connected to the second trigger input; the second input of the counter is connected to its output, the third input of the comparison circuit and the second input of the register; the outputs of the prediction block are connected to the third inputs of the register and to the first inputs of the ROM, the second input of which is connected to the output of the comparison circuit; the first outputs of the ROM are connected to the fourth inputs of the register, the second outputs of the ROM are connected to the third inputs of the counter, the third output of the ROM is connected to the third input of the trigger.

The disadvantage of this device is the ability to perform analog-to-digital conversion of signals of only positive polarity.

Utility Model Disclosure

The technical result that can be achieved using the proposed utility model is to expand the functionality.

The expansion of functionality consists in providing the possibility of analog-to-digital conversion of not only unipolar positive, but also unipolar negative and bipolar signals.

The technical result is achieved by the fact that in an analog-to-digital Converter containing: a comparison circuit; digital-to-analog converter (DAC); trigger; pulse generator; counter; register; read-only memory (ROM); a prediction block, and a DAC output connected to the second input of the comparison circuit, the inputs of which are connected to the outputs of the register, the second inputs of the prediction block, and the third inputs of the ROM; the second input of the device is connected to the first input of the register and the first input of the trigger, the output of which is connected to the first input of the prediction unit and the input of the pulse generator, the first output of which is connected to the first input of the counter, and the second output is connected to the second input of the trigger; the second input of the counter is connected to its output, the third input of the comparison circuit and the second input of the register; the outputs of the prediction block are connected to the third inputs of the register and to the first inputs of the ROM, the second input of which is connected to the output of the comparison circuit; the first outputs of the ROM are connected to the fourth inputs of the register, the second outputs of the ROM are connected to the third inputs of the counter, the third output of the ROM is connected to the third input of the trigger, a unit for determining the sign and inverting negative voltages (BOS and ION) is introduced, and the input of the BOS and ION serves as the input of the device, the first output of the BOS and ION serves as the first output of the device, the second output of the BOS and ION is connected to the first input of the comparison circuit; DAC inputs are connected to the second outputs of the device, and the trigger output is the third output of the device.

As a prediction block, a conventional register may be used. To implement a more accurate (linear) prediction algorithm, the prediction block (BPR) may contain two registers and a subtraction block, and the control inputs of the first and second registers are connected to the first input of the BPR, the second inputs of the BPR serve as information inputs of the first register, the outputs of which are connected to information inputs the second register and, taking into account the shift by one bit towards the higher digits, are connected to the first group of inputs of the subtraction unit, the second group of inputs of which are connected to the outputs of the second register, the output subtractor outputs are BDP.

BOS and ION contains an analog inverter, a comparator, a first (normally closed) analog key, a second (normally open) analog key; input BOS and ION is connected simultaneously to the input of the analog inverter, the first (non-inverting) input of the comparator, the signal input of the second (normally open) analog key; the second (inverting) input of the comparator is “grounded”; the output of the comparator is simultaneously connected to the first output of the BOS and ION and the control inputs of analog keys, the outputs of which are connected to the second output of the BOS and ION.

Brief Description of the Drawings

In FIG. 1, a block diagram of an analog-to-digital converter is shown.

In FIG. 2 is a block diagram of a prediction block.

In FIG. 3 is a block diagram of a unit for determining the sign and inverting negative voltages.

In FIG. 4 is a timing diagram explaining the operation of the unit for determining the sign and inverting negative voltages.

In FIG. 5 - algorithms for the code selection procedure.

Utility Model Implementation

The analog-to-digital converter contains a comparison circuit 1, a digital-to-analog converter (DAC) 2, a trigger 3, a pulse generator 4, a counter 5, a register 6, a read-only memory (ROM) 7, a prediction unit (BPR) 8, a sign determination and negative inversion unit voltages (BOS and ION) 9, moreover: the input of BOS and ION 9 serves as the input of the device ("U _I "), the first output of BOS and ION 9 serves as the first output of the device ("sign code"), the second output of BOS and ION 9 is connected to the first input of the comparison circuit 1; to the second input of the comparison circuit 1 is connected the output of the DAC 2, the inputs of which are connected to the outputs of the register 6, the second inputs of the Bpr 8, the third inputs of the ROM 7 and are the second outputs of the device ("amplitude code"); the second input of the device (“start”) is connected to the first input of register 6 and the first input of trigger 3, the output of which is the third output of the device (“completion of conversion”), and in addition, connected to the first input of Bpr 8 and the input of the pulse generator 4, the first the output of which is connected to the first input of the counter 5, and the second output is connected to the second input of the trigger 3; the second input of the counter 5 is connected to its output, the third input of the comparison circuit 1 and the second input of the register 6; the outputs of Bpr 8 are connected to the third inputs of the register bis the first inputs of the ROM 7, the second input of which is connected to the output of the comparison circuit 1; the first outputs of the ROM 7 are connected to the fourth inputs of the register 6, the second outputs of the ROM 7 are connected to the third inputs of the counter 5, the third output of the ROM 7 is connected to the third input of the trigger 3.

BPR 8 contains the first and second registers 10 and 11, a subtraction block 12, and the control inputs of the registers 10 and 11 are connected to the first input of the BPR 8, the second inputs of the BPR 8 serve as information inputs of the register 10, the outputs of which are connected to the information inputs of the register 11 and, with taking into account the shift by one bit in the direction of the higher digits, they are connected to the first group of inputs of the subtraction unit 12, the second group of inputs of which is connected to the outputs of the register 11, the outputs of the subtraction block serve as the outputs of Bpr 8.

BOS and ION 9 contains an analog inverter 13, a comparator 14, a first (normally closed) analog key 15, a second (normally open) analog key 16; input BOS and ION 9 is connected simultaneously to the input of the analog inverter 13, the first (non-inverting) input of the comparator 14, the signal input of the second (normally open) analog key 16; the second (inverting) input of the comparator 14 is “grounded”; the output of the comparator 14 is simultaneously connected to the first output of the BOS and ION 9 and the control inputs of the analog keys 15 and 16, the outputs of which are connected to the second output of the BOS and ION 9.

An analog-to-digital converter operates as follows.

BOS and ION 9 is designed to determine the sign (polarity) of the voltage level of the input signal and relay the input signal further with a unit transmission coefficient, and in the case of negative polarity, expose the translated inversion signal, that is, form the input signal module. ([3]. Patent RU 2356163, IPC Н03М 1/34; [4]. Khorolsky V.Ya., Bondar S.N., Bondar M.S. Increasing the efficiency of high-speed analog-to-digital converters by introducing a sign and inverting block negative stresses // News of Higher Educational Institutions. North Caucasian Region. Technical Sciences. - 2007. - No. 3. - P. 15-17.). In particular:

1) if a signal of positive polarity (time intervals [t ₁ ; t ₂ ], [t ₃ ; t ₄ ], (Fig. 4)) is received at the input of BOS and ION 9 (device):

- the comparator 14 generates a signal with a logical unit level (Fig. 4b);

- at the first output of the BOZ and ION 9 (the first output of the device ("sign code")) a signal is generated with the level of a logical unit (Fig. 4g);

- (normally open) analog switch 16 is put into a closed state;

- (normally closed) analog key 15 is put into an open state;

- the input signal is transmitted, through a closed analog key 16 (Fig. 4B), to the second output of the BOS and ION 9 (Fig. 4E);

2) in the case of a negative polarity signal (time intervals [t ₂ ; t ₃ ], [t ₄ ; t ₅ ], (Fig. 4)), received at the input of the BOS and ION 9 (device):

- the comparator 14 generates a signal with a logic level of zero (Fig. 4B);

- at the first output of the BOZ and ION 9 (the first output of the device ("sign code")) a signal is generated with a logic zero level (Fig. 4g);

- (normally open) analog switch 16 is put into an open state;

- (normally closed) analog key 15 is put into a closed state;

- the input signal inverted by means of an analog inverter 13 (Fig. 4d) is transmitted, through a closed analog key 15 (Fig. 4e), to the second output of the BOS and ION 9 (Fig. 4e).

Thus, BOS and ION 9 actually forms the module (1) (Fig. 4e) and the sign (2) (Fig. 4g) of the transmitted signal.

,

- выходное напряжение БОЗ и ИОН 9 на первом и втором выходах (U_вых1, U_вых2 - фиг. 4е, 4ж);Where

,

- the output voltage of the BOZ and ION 9 at the first and second outputs (U _o1 , U _oo2 - Fig. 4e, 4g);

U ¹ and U ⁰ - high and low voltage levels - logical unit and zero levels.

Comparison circuit 1 is intended to compare the module of the input converted voltage | U _I | and voltage from the output of the DAC 2 - U _DAC . In the case | U _BX |> U, the _DAC, at the output of the comparison circuit 1, a signal appears corresponding to a logical unit, otherwise, to a logical zero. As a comparison circuit 1, a gated comparator is used. When applying a zero level to its third (gate) input, the voltage at the output of the comparison circuit 1 is fixed.

The counter 5 is designed to form a time interval corresponding to the time of establishing the voltage at the output of the DAC 2 for the current code. To do this, a certain number is recorded in counter 5 and it is transferred to the subtraction mode. When applied to the first input of the pulse counter, its content decreases. After the contents of the counter reach a zero value, a logic zero level is set at its output, which signals the end of a specified time interval. The logical zero level from the output of the counter 5 goes to its second input, and it goes into recording mode. With the arrival of a positive front at the first input of the counter 5, information is recorded in it, submitted to its third (information) inputs. At the same time, at the output of counter 5, the level of the logical unit is set; it goes into subtraction mode and forms the next time interval. Suppose that for a given code K (fed to the input of the DAC 2), the time to establish the output voltage of the DAC 2 is T _i , and the period of pulses coming from the generator 4 is Δt, then for the formation of the time interval T _{i it} is necessary to write a code into the counter equal to N _CЧi = T _i / Δt. When describing the operation of the device, we assume that the delay is proportional to the difference between the previous code and the next (delay to establish the voltage at the output of DAC 2) plus one pulse for the duration of the comparison circuit 1. For example, if after code 8 (1000), the input of DAC 2 code 6 (0110), then in the counter 5 you need to write the number 3 (3 = 8-6 + 1).

Register 6 is designed to store the current value of the output conversion code. When a pulse is applied to the first input of register 6, information is written to it, fed to its third inputs from the output of PDU 8. On the positive edge of the pulse fed to the second input of register 6, information is written to it, which is fed to its fourth inputs from the first outputs of ROM 7 .

ROM 7 is intended for storing digital codes used in the process of selecting the output code corresponding to the input analog voltage module | U _I |. The ROM 7 also stores the delay values for all used codes (corresponding to the time of establishing the voltage at the output of the DAC 2).

BPR 8 is designed to select a search procedure depending on the codes obtained in previous conversion cycles. As BPR 8, a conventional register can be used. It will be used to memorize the code obtained in the previous conversion cycle (zero prediction algorithm). It is assumed that the input converted value will change slightly during the entire conversion cycle and, accordingly, the value of the output code in the next conversion cycle will be close to the value of the code in the previous cycle.

To implement a more accurate (linear) prediction algorithm, the structure of the BPR 8 may have the form shown in FIG. 2. In register 10, the code value obtained at the end of the last conversion cycle K _i is stored. This code will be written to the register 10 BPR 8 from the outputs of the register 6 of the device when a negative drop appears at the first input of the BPR 8 (from the output of trigger 3, at the end of the next conversion cycle). At the same time, the code from the output of register 10, i.e. code of the previous conversion cycle K _i-1 . Define the difference between the current and previous code value according to (3)

In accordance with the linear prediction algorithm, the following expected code value is determined according to (4):

The calculation according to the formula (4) is performed using the subtraction block 12, and the value of K _i is supplied to the first inputs of the subtraction block 12 from the output of the register 10 with a shift by one bit towards the higher digits. Thus, the multiplication of K _i by two is realized. At the second inputs of the subtraction unit 12, a code is supplied from the outputs of the register 11.

It should be noted that the first inputs of the ROM 7 and the third inputs of the register 6 are supplied with M high order bits of the calculation result by formula (4) from the output of the subtraction unit 12 (and, accordingly, from the outputs of the BPR 8, Fig. 2). In the general case, 1≤M≤N, where N is the resolution of the ADC. For M = N, it is necessary to make an optimal search procedure for all possible N codes of the bit ADC. This will require a significant amount of ROM 7. Given the inaccuracy of the prediction algorithm, it is advisable to use a value of M less than N, i.e. use one optimal code selection procedure for a group of output codes whose values are close to each other. The specific value of M is determined based on the accuracy of the prediction algorithm, the effectiveness of the code selection procedure, and on the basis of the restrictions imposed on the ROM capacity 7. Note also that for M <N, the free (lower) third inputs of register 6 are supplied with a logic zero level.

The task of constructing the optimal code selection procedure in the process of analog-to-digital conversion corresponds to the well-known task of constructing optimal diagnostic programs, i.e. search in the control object for a single faulty element ([5]. G. Pashkovsky. Tasks of Optimal Detection and Search of Failures in CEA / Edited by I. A. Ushakov. - M.: Radio and Communications, 1981. - P. 50 -84). In this case, it is necessary to find the only code value that is most suitable for the input converted voltage. Let, in accordance with the prediction algorithm used, the most probable next code value is the value 8 (1000). Then the optimal code selection procedure may be as shown in FIG. 5.

In accordance with FIG. 5 the first code to be checked is 8 (1000). If the voltage at the output of DAC 2 is greater than the input voltage module (| U _BX | <U _DAC ), then the following code 6 should be checked (0110) - the transition is made along the left branch of the graph, leaving the first vertex and marked with the number 0. If the voltage is the output of DAC 2 will be less than the input voltage (| U _BX |> U _DAC ), then the next code 10 (1010) should be checked - the transition is made on the right branch of the graph, leaving the first vertex and marked with the number 1. When reaching a hanging vertex or vertex , which has no left branch, the code selection process has ended etsya. In this case, the code indicated in FIG. 5 in the rectangle (to which the arrows fit). The rectangles to the right of the vertices of the graph indicate the delay for this code. Note that the codes closest to the most probable (for example, codes 6, 7, 9, 10) can be obtained in fewer steps than the values of the codes, less likely (for example, codes 0, 1, 14, 15).

The contents of the ROM area 7 for this code selection procedure are shown in the table.

The code selection procedure is recorded in ROM 7 as a sequence of words. Addresses of words are given in the second column "Address". The address value is given both in decimal and in binary (in brackets). The address consists of three parts. In the binary representation of the address in the table, the individual parts are separated by spaces. The older part of the address comes from the output of BPR 8 and for this code selection procedure it has the same value. The middle part of the address (1 bit) is formed by the signal from the output of the comparison circuit 1. The smallest part of the address is determined by the code coming from the output of register 6.

Each word has three fields. The first field "Code" contains the current code used at this step of selecting the output code (the table shows the decimal value of this code and in brackets its binary representation). The “Delay” field contains a number proportional to the time it takes to establish the DAC 2 and the comparison circuit 1 for the corresponding code from the “Code” field (in this case, it is assumed that this time is equal to the difference between the current code and the previous one plus one for the operation of the comparison circuit 1). Field "End sign" defines the time point for the end of the code selection procedure. The code selection procedure ends if this field contains one.

Consider the operation of the device with the following initial data. The resolution of the ADC is 4. The range for the bipolar input voltage module is 10 V (in the case of a bipolar input voltage symmetry, the input signal range can reach 20 V). For a 4-bit ADC, in this case, the quantization step is ΔU = 10 V / 2 ⁴ = 10 V / 16 = 0.625 V. This means that when a code is input to the DAC 2, for example, equal to 4, the voltage U _DAC = 4⋅0.625 = 2.5 V. Suppose that the input voltage module (the voltage coming from the second output of the BOS and ION 9 to the input of the comparison circuit 1) is 2.6 V (| U _BX | = 2.6 V), and as a prediction block, a regular register (zero prediction) is used.

Suppose also that from the outputs of the BPR 8 to the third inputs of the register 6 receives the code 8 (1000). This means that in the previous conversion cycle, using the zero prediction algorithm, code 8 (1000) was received. (When using the linear prediction algorithm, code 8 (1000) can be obtained, for example, if codes 6 and 7 or 4 and 6, etc., were received on the two previous conversion clocks). Code 8 (1000) will also go to the first (senior) inputs of the ROM address 7, i.e. the memory area of ROM 7 will be selected, where the code selection procedure is written for the case when the most probable value in the next cycle of analog-to-digital step conversion is code 8 (1000).

At counter 5, at the end of the previous conversion cycle, a code should be written that is generally equal to the difference between the output code obtained in the previous conversion cycle and the value of the code that will be used first in the search procedure on the next conversion cycle. If a different search program is compiled for each predicted code (all bits of prediction block 8 are connected to the first inputs of ROM 7, i.e., M = N) and a zero prediction algorithm is used, then the contents of counter 5 should be equal to one, since the value of the code at the input DAC 2 will not change and there is no need to introduce a delay for DAC 2, you only need to take into account the delay of the operation of comparison circuit 1. (When you turn on the device, counter 5 must contain the maximum value, and register 6 must be arbitrary - this can be achieved by special and preset circuits not shown in Fig. 1).

In the initial state, trigger 3 is in the zero state. To start the next cycle of analog-to-digital conversion, a short pulse is applied to the second input of the Start device, which is fed to the first input of register 6, due to which the code from the output of BPD 8 will be written into it, in this case code 8 (1000). The code of the number 8 (1000) from the output of register 6 will go to the input of the DAC 2 and the voltage U of the _{DAC will be} set at its output = 8ится0.625 = 5 V. This voltage will go to the second input of the comparison circuit 1, the first input of which is supplied with the input conversion voltage module (for example, | U _BX | = 2.6V). Since | U _BX | <U _DAC , the output corresponding to the logic zero will appear at the output of the comparison circuit 1.

The start pulse from the second input of the Start device will also go to the first input of trigger 3, under the influence of which trigger 3 will go into a single state. At the output of trigger 3, the level of the logical unit is set, which will go to the third output of the device, signaling the beginning of the next conversion cycle. A single signal from the output of trigger 3 will also go to the control input of the pulse generator 4, which will begin to generate rectangular pulses. The pulses from the first output of the pulse generator 4 will begin to arrive at the first input of counter 5. Since the contents of counter 5 are nonzero (as mentioned earlier, the contents of counter 5 at the beginning of the conversion cycle is unity), the signal of a logical unit from its output goes to its second input, those. counter 5 is set to subtract. On the positive front of the next pulse from the output of the pulse generator 4, the contents of the counter 5 will decrease by one and become equal to zero. During this time, transients in comparison scheme 1 will end. The zero level from the output of counter 5 will go to the third (gating) input of the comparison circuit 1, fixing the value of the signal at its output so as to exclude its change when overwriting information from ROM 7 in register 6 and counter 5.

Thus, at the address inputs of the ROM 7 will be generated code 264 (1000 0 1000). In this case, at the first outputs of ROM 7, the code of the number 6 (0110) will appear, at the second outputs - the code of the number 3 (0011) and at the third output - the zero level (9th line in the table). Since when counter 5 is reset to zero, it goes into recording mode, with the arrival of the next pulse from the first output of the pulse generator 4 to the first input of the counter, the code of the number 3 (0011) from the second outputs of the ROM 7 will be written into it. The contents of counter 5 will become non-zero and A positive voltage drop will be formed at its output, according to which a code of 6 will be written in register 6 from the first outputs of the ROM 7. In FIG. 5, this corresponds to the transition from code 8 to code 6 for | U _BX | <U _DAC .

At the output of the DAC 2, the voltage U _DAC = 6 В0.625 = 3.75 V will appear and since | U _BX | <U the _DAC , the logic zero level will be established at the output of the comparison circuit 1. The code 262 (1000 0 0110) will be set on the address inputs of the ROM 7 and the code 4 (0100) will appear on the first outputs of the ROM 7, and the code 3 (0011) on the second outputs (7th line in the table). After resetting counter 5, code 4 (0100) will be recorded in register 6, and the contents of counter 5 will become 3 (0011).

At the output of DAC 2, the voltage U _DAC = 4⋅0.625 = 2.5 V. will appear. Since in this case | U _BX |> U _DAC , the level of the logical unit will be established at the output of comparison circuit 1. On the address inputs of the ROM 7, the code number 276 (1000 1 0100) will be set and on the first outputs of the ROM 7 the code 5 (0101) will appear, and on the second outputs the code 2 (0010) (the 21st line in the table). After resetting counter 5, code 5 (0101) will be recorded in register 6, and the contents of counter 5 will become equal to 1 (0001).

At the output of DAC 2, the voltage U _DAC = 5⋅0.625 = 3.125 V appears. Since in this case | U _BX | <U _DAC , the logic zero level is set at the output of comparison circuit 1. On the address inputs of ROM 7, the code of the number 261 (1000 0 0101) will be set, and code 4 (0100) will appear on the first outputs of ROM 7, and code 1 (0001) on the second outputs (6th line in the table). After resetting counter 5, code 4 (0100) will be recorded in register 6, and the contents of counter 5 will become equal to 1 (0001).

At the same time, the logical unit level (the 6th row in the table, the column "End sign") will be set at the third output of ROM 3, which will go to the third input of register 3, so that with the arrival of the pulse from the second output of the pulse generator 4, trigger 3 will go to zero state. At the output of trigger 3, a logic level of zero will be established, which will go to the third output of the device, signaling the end of the next cycle of analog-to-digital conversion. According to the negative difference at the output of trigger 3, the result of the last conversion, in this case code 4 (0100), will be recorded in BPR 8. When using the zero prediction algorithm, code 4 (0100) from the output of prediction block 8 will be fed to the upper bits of the ROM 7, and thus, in the next conversion cycle, the code selection procedure from another memory area of the ROM 7 will be used.

The zero level from the output of trigger 3 will also suspend the operation of pulse generator 4. In this case, the contents of counter 5 will be 1 (0001), i.e. the device will be prepared for the next analog-to-digital conversion cycle.

We determine the conversion time for the proposed ADC. In FIG. 5 next to the vertices of the graph (on the right) are the delay values for each tested combination (the delay values are enclosed in a rectangle). The delay values are defined as the number of pulses that should come from the output of the pulse generator 4 to counter 5 to verify this code. It is equal to the value of the delays shown in the table for each code, plus one pulse necessary for overwriting information from ROM 7 into counter 5 and register 6. Under the above conditions and using the selection procedure, the graph of which is shown in FIG. 5, the greatest delay will be if the following output codes are 0, 1, 14 or 15. So, for code 0, you will need to check codes 8, 6, 4, 3, 2, 1. The total delay will be 2 + 4 + 4 + 3 + 3 + 3 = 19 pulses.

When using a conventional sequential approximation ADC, for any output code, it is necessary to check four codes for a 4-bit ADC. The delay is 15⋅4 = 60 pulses. In the proposed device - 15 pulses.

The ADC device, which serves as a prototype, is focused on working with unipolar signals (signals of positive polarity). Due to the introduction of BOS AND ION 9 into the device, the proposed ADC device can work with both unipolar signals (both positive and negative polarity) and bipolar signals, that is, there is an extension of the functionality of the proposed ADC device relative to the prototype.

Claims (1)

An analog-to-digital converter, comprising: a comparison circuit; digital-to-analog converter (DAC); trigger; pulse generator; counter; register; read-only memory (ROM); a prediction block, and a DAC output connected to the second input of the comparison circuit, the inputs of which are connected to the outputs of the register, the second inputs of the prediction block, and the third inputs of the ROM; the second input of the device is connected to the first input of the register and the first input of the trigger, the output of which is connected to the first input of the prediction unit and the input of the pulse generator, the first output of which is connected to the first input of the counter, and the second output is connected to the second input of the trigger; the second input of the counter is connected to its output, the third input of the comparison circuit and the second input of the register; the outputs of the prediction block are connected to the third inputs of the register and to the first inputs of the ROM, the second input of which is connected to the output of the comparison circuit; the first outputs of the ROM are connected to the fourth inputs of the register, the second outputs of the ROM are connected to the third inputs of the counter, the third output of the ROM is connected to the third input of the trigger, characterized in that a unit for determining the sign and inverting negative voltages (BOS and ION) is introduced into the device, and the input of the BOS and ION serves as the input of the device, the first output of the BOS and ION serves as the first output of the device, the second output of the BOS and ION is connected to the first input of the comparison circuit; the DAC inputs are connected to the second outputs of the device, and the trigger output is the third output of the device; BOS and ION contains an analog inverter, a comparator, a first (normally closed) analog key, a second (normally open) analog key; input BOS and ION is connected simultaneously to the input of the analog inverter, the first (non-inverting) input of the comparator, the signal input of the second (normally open) analog key; the second (inverting) input of the comparator is “grounded”; the comparator output is simultaneously connected to the first output of the BOS and ION and the control inputs of analog keys, the outputs of which are connected to the second output of the BOS and ION; the output of the analog inverter is connected to the signal input of the first (normally closed) analog switch.

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