SG81954A1 - Microprocessor with improved out of order support via register management with synchronization of multiple pipelines - Google Patents

Microprocessor with improved out of order support via register management with synchronization of multiple pipelines

Info

Publication number
SG81954A1
SG81954A1 SG9900135A SG1999000135A SG81954A1 SG 81954 A1 SG81954 A1 SG 81954A1 SG 9900135 A SG9900135 A SG 9900135A SG 1999000135 A SG1999000135 A SG 1999000135A SG 81954 A1 SG81954 A1 SG 81954A1
Authority
SG
Singapore
Prior art keywords
microprocessor
synchronization
support via
multiple pipelines
order support
Prior art date
Application number
SG9900135A
Inventor
J Heller Thomas Jr
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to SG9900135A priority Critical patent/SG81954A1/en
Publication of SG81954A1 publication Critical patent/SG81954A1/en

Links

SG9900135A 1999-01-21 1999-01-21 Microprocessor with improved out of order support via register management with synchronization of multiple pipelines SG81954A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG9900135A SG81954A1 (en) 1999-01-21 1999-01-21 Microprocessor with improved out of order support via register management with synchronization of multiple pipelines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG9900135A SG81954A1 (en) 1999-01-21 1999-01-21 Microprocessor with improved out of order support via register management with synchronization of multiple pipelines

Publications (1)

Publication Number Publication Date
SG81954A1 true SG81954A1 (en) 2001-07-24

Family

ID=20430261

Family Applications (1)

Application Number Title Priority Date Filing Date
SG9900135A SG81954A1 (en) 1999-01-21 1999-01-21 Microprocessor with improved out of order support via register management with synchronization of multiple pipelines

Country Status (1)

Country Link
SG (1) SG81954A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574349A (en) * 1981-03-30 1986-03-04 International Business Machines Corp. Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction
US4901233A (en) * 1987-07-20 1990-02-13 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
US5559976A (en) * 1994-03-31 1996-09-24 International Business Machines Corporation System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions
US5751981A (en) * 1993-10-29 1998-05-12 Advanced Micro Devices, Inc. High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574349A (en) * 1981-03-30 1986-03-04 International Business Machines Corp. Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction
US4901233A (en) * 1987-07-20 1990-02-13 International Business Machines Corporation Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
US5751981A (en) * 1993-10-29 1998-05-12 Advanced Micro Devices, Inc. High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format
US5559976A (en) * 1994-03-31 1996-09-24 International Business Machines Corporation System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions

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