SU1107286A1 - Device for automatic digital control of gain factor - Google Patents

Abstract

DEVICE FOR AUTOMATIC discrete control GAIN comprising serially connected discrete controllable attenuator, an analog-digital converter, comparing elements and the second register, and the clock generator, characterized in that, in order to increase its speed, between the output of the first register and the control in; soda discrete controlled attenuator included serially connected code converter, adder and second register J between the output of the clock generator and the input The synchronization house of the second register includes a delay element, the input of setting the zero of the first register is connected to the output of the clock generator, the information input to the output of the analog-digital converter, the output to the second input of the comparison element, and the output of the second register are connected to the second input of the adder.

Description

The invention relates to radio engineering and can be used in automation systems, communications and medical instrumentation.

A device for automatically discretely adjusting the gain is known, comprising an amplifier, a controlled resistive matrix and a serially connected between the outputs of the amplifier and the control inputs of a controlled re-active matrix a multi-digit converter of amplitude value of voltage into a code, a digital discriminator and an N-parallel reversible counter I.

The disadvantage of the device is low speed.

The closest in technical essence to the invention is a device for automatic discrete gain control, containing a serially connected discrete controlled attenuator. the analog-to-digital converter, the comparison unit and the first register, and also the clock generator 2. However, the known device does not have a sufficiently high speed. The purpose of the invention is to increase the speed. The goal is achieved by the fact that the automatic discrete gain control device containing a serially connected discrete controlled attenuator, an analog-to-digital converter, a comparison element and a first register, as well as a clock generator, is connected between the output of the first register and control inputs of the discrete controlled attenuator serially connected code converter, adder and second register between the output of the clock generator and the synchronization input of the second the register includes a delay element, the input of setting zero of the first register is connected to the output of the clock generator, the information input is connected to the output of the analog-digital converter, the output is connected to the second input of the comparison element, and the output of the second register is connected to the second input of the adder. The drawing shows a structural electrical circuit of the proposed device. The automatic discrete gain control device contains

discrete controlled attenuator 1, analog-to-digital converter (ADC) 2, reference clock generator 3, 4, first register 5, delay element 6, code converter 7, adder 8, and second register 9.

The device works as follows.

The discrete controlled attenuator 1, consisting of, tg series-connected dividers 1 ... 1 ru, receives an analog signal of arbitrary shape at the input. The transfer ratio of each divider is determined by

V4

expression, where, 2 .., m is the number of the divisor;

K is the transmission coefficient of the first divider, which determines the specified point of the installation of the amplitude of the output signal, expressed in dB. Thus, in the enabled state, the transmission coefficient of each subsequent divider is equal to the square of the previous transmission coefficient. From the output of the discrete controlled attenuator 1, the signal is fed to the input of the A / D converter 2, from whose output the digital code is fed to the first input of the 4th comparison and the information input from the first register 5, the output of which is connected to the second input of the 4th comparison. When the current code received from the A / D converter 2 is exceeded over the code stored in the first register 5, the comparison element 4 generates a control pulse input to the synchronization input of the first register 5. Thus, at the end of the device operation period determined by the pulse period clock generator 3 arriving at the input of the zero setting of the first register 5, the first register code 5 contains the code of the maximum amplitude of the signal, I go (Iu further to the code converter 7. Code converter 7 generates a binary control code The quencher / Vjc. in accordance with the expression N.integer (, 5), where N4 is the code of the maximum signal amplitude; N & a is the signal reference level code Constant value 0.5 is entered to eliminate the systematic error when performing the operation of the whole parts from the above expression. From the output of the code converter 7, the control code for the attenuator L1 is fed to the first input of the adder 8. In the adder 8, the control code for the attenuator jVff is made with the value of the control code for the discrete controlled attenuator 1 stored in the second register 9, which leads to a decrease in the value of the increase in the transfer coefficient of the discrete controlled attenuator 1 by the amount necessary to set the amplitude of the signal to be equal to the reference level. Writing to the second register 9 is carried out by pulses from the clock generator 3 through the delay input element 6 of the second register 9 synchronization, the delay value determines the time for selecting the maximum signal amplitude. Thus, setting the transmission coefficient with a predetermined accuracy determined by the transmission coefficient of the first divider I discrete controlled attenuator 1, in the proposed device, is performed in just one working cycle. However, at the moment the device is turned on or when random noise occurs, situations are possible in which the code of the maximum signal amplitude in the first register 5 is -2 least significant bits, and the measurement error of the maximum signal amplitude can reach 50%, which leads to the same error in setting the signal, and in order to set the required transmission coefficient in this case, one additional clock cycle will be required, or the first register 5 may be set to the maximum code position; 7 a code converter control kbda discrete controllable attenuator 1 corresponding to the minimum transmission ratio, resulting in h-his situation may occur first, and in this case to set the desired transmission ratio will be required three cycles of operation. The proposed device makes it possible to set the required transfer rate of the ssegb per cycle during normal operation of the device and not more than three cycles in the event of a faulty situation, while setting all dividers of the discrete controlled attenuator 1 is performed simultaneously, and the speed does not depend on the resolution device.

Claims (1)

DEVICE FOR AUTOMATIC DISCRETE ADJUSTMENT OF THE AMPLIFICATION CODE, containing a discrete controlled attenuator, an analog-to-digital converter, a comparison element and a first register, as well as a clock generator, characterized in that, in order to increase its speed, between the output of the first register and the control inputs of the discrete controlled attenuator included in series connected code converter, adder and second register, between the output of the clock generator and the input of syn ronizatsii second register included delay element, the set input of the first register is connected to the output of zero clock, information input - to the output of analog-converter output to the second input of the comparison element, and an output of the second register is connected to the second input of the adder.