SU1432502A1 - Device for comparing numbers - Google Patents

Abstract

The device relates to computing and a knife to be used in data transmission systems with data compression, as well as in digital signal processing devices. The purpose of the invention is to expand the functionality of the device by providing the ability to compare numbers with the tolerance. The device for comparing numbers contains two matrices of summing cells 1, 2, tolerance register 3, block 5 of buffer memory, reference number register 6, groups of summing cells 7, 8. The device compares numbers with tolerance, realizing the ratio / ai -b / r cf Computational operations and operations of comparing numbers with a tolerance in the proposed device are performed in parallel-conveyor mode 2 sludge. I (L

Description

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The invention relates to the computational technique and can be used in telemetry data transmission systems with data compression HbiXj as well as in digital signal processing devices.

The purpose of the invention is to expand the functionality of the device by comparing the numbers with the tolerance

i FIG. 1 is a diagram of a device for comparing numbers in FIG. 2 - the circuit of summing-up cells is functional

The comparison device contains matrices 1 and 2 of summing cells, tolerance register 3, summing cell 4, buffer memory block 5, reference number register 6, group 7 and 8 summing cells, output 9 digit bits of the device

The summing cell 4 contains the element AND 10, the element ISKSHOTCHAMEYE OR 11 and two triggers 12 and

A device for comparing numbers with a tolerance realizes the ratio

/ at- b /: cf.

the first inputs of the summing cells of group 7, the second inputs of which, as well as the second input of the (2, n) -th cell of the first matrix, receive a signal from the inverse output of the (n, 1) -th summing cell of the second matrix, From the output of the summing cells of group 7, the number S, written in the additional code, goes to the first inputs of the first row of cells of the first matrix. The second inputs of the first row of the matrix 1 are connected to the output of the register 3 tolerance.

The first matrix 1 performs the operation of adding the tolerance S and the result of summing the reference number b with a. The work of the first matrix is similar to the work of the second matrix

When at the output 9 of the sign bit, which is the output of the device for comparing numbers, the signal and, consequently, 1a - b1, a signal 1 is sent to the record control input of the register 6, which switches the register to the record of the number a.

Claims (1)

Invention Formula  The device works as follows. The second matrix 2 performs summation of the number with the number b, the n-bit number a, received by the input group, and converted into an additional code in group 8, summing cells of the 0th row and (2, p) -th bus of the logical unit is fed to the first inputs of cells 4 of the first row of the first matrix. The second inputs of the summing {their cells of the first row are connected to the outputs of the register Triggers 12 and 13, which are included in cells 4, memorize the result of summation and transfer for the time of one clock cycle. With the arrival of each next clock pulse, a bus enters a new input number codes, and (i, j; -e cells, where, ... n, j 1, .., n, produces the cyMMHposaHJie amount received in the previous cycle in the cell of the same column (1-1) -th row with the transfer from the cell (j + 1) -th column, (1-1) -th row. Thus, the operation of the shunting operation is performed in the parallel-conveyor relative . The result of summing the number b with the number a — the number S arrives at A device for comparing numbers that contains the first matrix of n summing cells, where n is the width of the input numbers, the output of the sum (summing cell of the matrix (i is the row number of matrides), ... n-l; j is the column number of the matrix,,. ,, n, and is connected to the first input (i + 1 ,. j) of the summing cell of the matrix, the transfer code (,) of the summing cell matrix, where g 2 ,,,., p, is connected to the second input of the corresponding C + 1, 5-1) -th north side of the mimic cell of the matrix ;, the second inputs (k, n) -x of the summing cells of the matrix, where k 3 ,, .P. 0 g are connected to the input of the logical zero of the device, the output of (n, 1 -) - th sum of the supply cell of the matrix is the output of the sign bit of the device, characterized in that, in order to expand the functionality of the device by comparing the numbers the first and second groups of summing cells are entered into it, the second matrix of n sum- #- {ruyun their cells, the buffer memory block, the register of the reference number, the tolerance register, the bits of which are connected to the first inputs of the sum of their first group cells, the second whose inputs are connected to The outputs of the sum of the corresponding summing cells of the second group, the first inputs of all the summing cells of the second group are connected to the second input (2, p) -A of the summing cell of the first matrix and with the inverse output of the sum of the (n, 1) -th summing cell of the second matrix, the outputs of summing cells the pth row of which is connected to the second inputs of the corresponding summing cells second group, exit (1,) - nd The summing cell of the second matrix is connected to the first input of the corresponding (i + 1, j) -and the summing cell of this matrix, the transfer output (i, g) - the summing cell of the second matrix is connected to the second input of the corresponding (.1 + 1, g-1) th sum432502 modulating cells of this matrix, the second inputs are (k, n) -x summing cells. the second matrix is connected to the input of the logical zero of the device, the second input (2, n} -th summing cell of the second matrix and the first inputs of the summing cells of the first group are connected to the input of the logical unit, The fO devices, the second inputs of the summing cells of the second group are the inputs of the device number and are connected to the inputs of the corresponding bits of the buffer memory block, the information outputs of which are connected to the information inputs of the reference number register, the recording control input of which is connected to the output (n, 1) th summer cell first 2Q matrices. .2 6,