SU1640744A1 - Multichannel memory with redundancy - Google Patents

Abstract

The invention relates to computing and is intended for use in devices of increased reliability, in particular for storage devices of specialized computers. The aim of the invention is to increase the reliability of the device. Each channel of a multichannel backup storage device contains a storage unit 1, a comparison unit 4, a control unit 8, a switch 13, a first 14 and a second 17 modulo two adders, a register 15, and a group of elements 16, the invention improves the reliability of the device by introducing a separate single bit reservation. When a single channel accumulator fails in the device, the failed bits are restored by comparing with the information of the healthy channel. If the failed bits appear in several channels, then their recovery is accomplished by introducing temporal redundancy and an additional comparison operation with the modified information. 2 tab., 3 Il. cl

Description

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The invention relates to computing and is intended for use in devices of increased reliability, in particular for storage devices of specialized computing machines.

The purpose of the invention is to increase the reliability of the device.

FIG. 1 shows a block diagram of a single channel of a multi-channel reserved storage device; in fig. 2 - structural removal of a three-channel backup memory device; in fig. 3 is a control block diagram.

Each channel of the multi-channel backup memory device contains a storage device 1, the inputs of which are information inputs 2 channels, and outputs 3 storage 1 are connected to the inputs of the first group of comparator unit 4, consisting of the group of modulators 2 modulo 2 and elements IL & 6, and the inputs of the second group are the inputs 7 of the comparator unit 4, the control unit 8 connected to the outputs 9 and 10 and the inputs 11 and 12 of the channel, the switch 13, the first group of adders 14 modulo two, the register 15, the group of elements And 16, the second adder group 17 on mo There are two of them, outputs 18 of which are channel informational outputs. The outputs 19 of the switch 13 are the outputs of the channel, the input 20 of the control unit 8 is the control input of the channel, and the output 21 of the control unit 8 is the control output.

The redundant three-channel storage device (Fig. 2) has an annular structure, with the outputs 19 of each channel connected to the inputs 7 of the subsequent channel (counting is clockwise). The outputs 9 and 10 of each channel are connected respectively to the input 12 of the previous one and the input 11 of the subsequent channel.

The control unit 8, which is connected to the control input 20 of the channel and with the subsequent output 21 (Fig. 3), consists of the decoder 22, the AND 23 element, the four-input OR 24 element 24, the trigger 25, the first delay element 26 and the second element 27 delay, the first element OR 28, the majority element 29 and the second element OR 30.

Redundant storage device operates as follows.

The inputs 2 of each channel receive information from the corresponding channel of the redundant digital computer. From the outputs 3 of the accumulator 1 of each channel, the information enters the comparison block 4 and through the switch 13 enters the input 7 of the block

comparing the subsequent channel. The input of the unit 4 for comparison of the channel of the same name receives information from the outputs 19 of the previous channel. If the information is the same in all channels, then the Log.O level will be set at the output of the comparison block 4 of each channel. At the same time, the inputs of the register 15 and the inputs of the element 16 also establish the levels of the Log.O.

Signals See Ci, Ci + i at the inputs of the control unit of each channel will have a level of Log.O11, which corresponds to output set 1 (Table 1). At the same time, block 8 of control will keep signal 01 equal to Log.1 and signal 02 equal to Log. ABOUT. Thus, after the arrival of the control signal, which corresponds to the establishment of Log 0 at the input 20 of the device, writing to the register 15 will not occur and the switch 13 will remain in the initial state. After the delay time Ti, the output control signal will be generated in the form of setting the Log.O level at the output 21 of the device. This signal accompanies the information at output 18, which will pass through a group of modulo-17 adders unchanged.

Similar actions in a healthy channel are performed with input sets 2 and 3 (Table 1), which corresponds to the occurrence of an error in one of the adjacent channels. If an error occurs in the accumulator of the same name channel, the set 4 will be formed at the inputs of the decoder 22 of the control unit 8 of this channel (Table 1). In this case, after a delay time, a signal Q2 will be issued in the form of a positive polarity pulse, which is removed after the input control signal is removed. By signal 02, the code from Log.1 in the position of the failed bits will be entered in channel 15 register. The same code is present at the outputs of the element And 16 and enters the first inputs of the group of adders 17 modulo two. As a result, the information output of channel 18 will result in the inversion of those bits that differed from the bits of the previous channel that was in service. Thus, at the moment of outputting the output control signal, the recovered information is present at the outputs 18.

If errors occur in the accumulators of two or three channels, incomparison of information will occur in all blocks 4 of the comparison, therefore, at the inputs C, Ci, CI-M of the control block 8 each Channel contains all Log.1. The outputs of the decoder 22 are set to the state corresponding to set 5 (Table 1). In this case, after a time delay, the register 25

3 and decoder 22, and output 02 generates a write signal to register 15. Level nLog.1 at the inverse output of flip-flop 25 will block premature output of the output control signal upon further switching. The information from output 3 of accumulator 1 passes through a group of adders 14 modulo two, where those bits that are not compared in block 4 of comparison are inverted and fed to the inputs of switch 13. After a delay time n + T2, a level Log is generated at output Qi O about which the switch 13 is switched, and from its output to the block 4 for comparison of the subsequent channel enters modified information. Modified information from the previous channel also arrives at the input of unit 4 comparing the channel of the same name. As a result of re-comparing it with the channel information at the inputs of the element 16, a code will be formed with units in incomparable bits. At the outputs of the element And 16 installed mc Log. G in those categories that have not been compared both in the first and in the second comparison. The resulting mask, arriving at the first inputs of adder groups 17 modulo two, will cause the inversion of the corresponding bits at output 18. Thus, information will be restored on the principle two out of three. The states of the inputs and outputs of the channel blocks are given in Table 2 for an example of a 4-bit word. 2

The technical and economic advantages of the proposed device are to increase the uptime of the device by reducing the scale of the backup of the storage device to the level of one bit.

Claims (1)

Multi-channel redundant storage device containing in each channel a drive, a comparison unit, a control unit, a switch, information inputs of the first group of which are connected to the outputs of the storage device and inputs of the first group of the comparison unit, the output of which is connected to the next control unit channel, with the third input of the mode setting of the control unit of the subsequent channel and with the first input of the mode setting of the control unit of this channel, the second and third inputs of the mode setting of which are connected with the outputs of the comparison units of the previous and subsequent channels, respectively, the first output of the control unit is connected to the control input of the switch, the accumulator inputs are informational the inputs of this channel of the device, characterized in that, in order to increase the reliability of the device, each of its channels includes a group of elements AND, the first and second groups of modulators two, a raster, whose inputs are connected by the outputs of the comparison unit and with the inputs of the first group of elements AND groups, the inputs of the second group of which are connected to the outputs of the register and with the inputs of the first group two moduli of the first group, the inputs of the second group of which are connected to the outputs of the accumulator and the inputs of the second group of modulators modulo two of the second group, the inputs of the first group of which are connected to the outputs of the AND elements of the group, the outputs of the modulo-two adders of the second group are information outputs of the channel, the outputs of the modulo-adders two of the first group are connected to informational the inputs of the second switch group, the outputs of which are connected to the inputs of the second group of the next channel comparison unit, the inputs of the second group of the comparison unit are connected to the switch outputs of the previous channel, the synchronization input of the control unit is the control input of this device channel and the synchronization input which is connected to the second the output of the control unit, the third output of which is the control output of the channel of the device. twice unmatched bit Table 1 Table 2 # 20 C, d Ct.,