SU1674221A1 - Data display unit - Google Patents

Abstract

The invention relates to computing and can be used in control systems for outputting information from a digital computer. The purpose of the invention is to increase the speed of the device. The device contains a memory management unit 1, a control unit 2, a synchronization unit 3, the first group of multiplexers 4.1 - 4.N, the first group of elements AND 5.1 - 5.N, the group of memory blocks 6.1 - 6.N, the first group of registers 7.1 - 7.N, the second group of registers 8.1-8.N, selection block 9, video signal generator 10, television indicator 11 with corresponding links. The introduction of the memory management unit 1, the first group of multiplexers and the first group of elements I provided the ability to dynamically redistribute the modes of the memory blocks when one of them works in the recording mode and the others in the information reading mode, which allows to increase the device speed during output dynamic images. 5 il.

Description

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The invention relates to computing and can be used in control systems for outputting information from a digital computer.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 is a functional block diagram of the control unit; FIG. 3 is a functional block diagram of the memory management unit; in fig. 4 - functional block selection scheme; in fig. 5 is a functional diagram of a video signal conditioner.

The device comprises a memory management unit 1, a control unit 2, a synchronization unit 3, a first group of multiplexers 4, a first group of elements 5 I, a group of blocks of 6 memory, a first group of registers 7, a second group of registers 8, a block 9 of selection, a video signal generator 10 , television indicator 11.

The control unit 2 contains the first counter 12, the first element 13 AND, the first element 14 AND-NOT, the first shift register 15, the address register 16, the data register 17, the second AND-NOT element 18. the second element is 19 And, the second shift register 20, element 21 is NOT. the second counter 22, the third element 23 AND, the third counter 24, the first 25 and second 26 elements OR, the fourth counter 27. the fourth element 28 AND, the third 29 and the fourth 30 elements OR.

The memory management unit 1 contains the third shift register 31, the first 32 and second 33 registers, multiplexer 34, first decoder 35, third register 36, second decoder 37, third group of registers 38, fourth register 39, second group of multiplexers 40, third group of multiplexers 41, third decoder 42, fifth register 43.

Block 9 of the selection contains the fourth group of multiplexers 44, the fifth group of multiplexers 45, the sixth 46 and the seventh 47 registers.

The video shaper 10 contains the first group of elements 48 NOT, the second rp / num of elements 49 and the fifth element 50 OR, the second group of elements 51 NOT. the third group of elements 52 I, the sixth element 53 OR, the element 54 2-2I-OR-NO

The positions 55-73, 74-83, 84-93 94-98 denote the inputs and outputs of the control unit 2 of the memory control unit 1, the selection unit 9 and the video signal generator 10, respectively.

The device provides the ability to dynamically redistribute the modes of operation of the memory blocks 6, when one of them operates in the recording mode, and the rest

- in the mode of reading information, which increases the speed of the device when displaying dynamic images.

The device works as follows.

According to the initialization signal 74 of the unit 1, the multiplexer 34 connects the outputs of the K-bit register 32 to the corresponding inputs of the registers 38.138 .N-1 and sets To the bit register 39 and the register 36 to the state of the logical unit. According to the synchronization signal, commands 75 and 76. The 2K bits of the command are rewritten as follows: in register 32, the first K bits in the second synchronization signal 76 and in the register 33 are the second K bits, in the first synchronization signal 75. in addition, on the shift register

31 a sequence of clocks is formed with a duration equal to the period of the clock frequency (input 79)

To team bits from register output

32 enter the input of the decoder 35 and through the multiplexer 34 to the inputs of the register

36 and registers 38 1-38N-1. The bits of the command from the output of the register 33 arrive at the address inputs of the multiplexers 40 1-40.К. The second clock from the shift register 31 enters the gate input of the decoder 35 and the synchronization signal of one of the registers 38.1-38.N-1 appears at the corresponding output of the decoder. By this signal, the K-bit code from the input of the registers 38 1-38 N-1 is rewritten into one of these registers.

Thus, according to the setup signal to the original and the filing of N-1 synchronization signals and N-1 "-discharge commands, an initial order distribution occurs.

memory blocks according to the type of information stored in them and setting the N o th memory bank to record mode

N outputs of the decoders 37 and 42 control the connection of the address bus and signals

control from control block 2 through 4.1-4 N multiplexers and elements 5 to the corresponding memory blocks 6

After removing the CHI setup, the device is ready for operation.

The number of registers 38.1-38.N-1 corresponds to the number of information layers simultaneously displayed on the indicator screen, each of them contains a physical code (number) of the memory block forming the information layer.

From the external interface unit on the synchronization signal 76 to the register 32 is the recording of the code of one of the registers.

38.1-38.N-1. On the same synchronization signal, register 31 is triggered.

The second clock from the shift register 31 selects the signal at the corresponding output of the decoder 35 and writes to one of the registers 38.1-38.N-1 the data stored in the register 39, entering the input of these registers through the multiplexer 34, controlled by the signal Set to initial state.

The third clock cycle is the rewriting of information from register 43 to register 39.

In addition, the synchronization signal 75 from the external interface unit records information in the register 33. The output information of the register is the address of multiplexers 40.1-40. To pass information from one of the registers 38.1-38.N-1 to the decoder 42, which is allocated There is no signal to allow the passage of the recording signal (elements 5.1-5.N) to one of the blocks b. 1-6.N memory.

In control block 2 (Fig. 2), the necessary control signals and an address for cyclic reading from information memory blocks synchronously with a television scan are generated from the synchronization signals on the frame, row and clock frequency coming from the synchronization block.

The counter 12 and the element 13 form a clock start signal for generating control signals on the shift registers 15 and 20 for the memory blocks operating in the write and read mode. Elements 18 allow the trigger signal to pass to the serial input of the shift register 20 only during the time determined by the synchronization signals in the row and frame, which allows generating the necessary control signals by elements 25 and 26 and enumerating the ads on the counter 27 synchronously with the regular television scan . Element 19 generates the passage of the clock frequency only during the time determined by the synchronization signals for the row and frame to synchronize the odd shift registers 7.1-7.N of the selection unit 9, unit 10 and the counter 22 and the control element 23 for the write control signal for the above shift registers . Element 21 does NOT form an inverse clock frequency for synchronization of even-numbered shift registers 8.1-8. N of selection unit 9, block 10 and generation of a control signal for the corresponding shift registers by counter 24 and 23 L.

The address (55) and data (56) from the interface device, arriving respectively at registers 16 and 17, are accompanied by a request signal (57), which, at the input

element 14 of control unit 2, permits the passage of a trigger signal from element 13 AND to the serial input of the shift register 15. This allows the necessary control signals for the memory unit operating in the elements 29 and 30 OR and the fifth output of the shift register 15 to be generated. recording mode, as well as the response signal to the interface device and the synchronization of writing to registers 16 and 17

5, respectively, from the second and first outputs of the shift register 15. The control signals from the outputs of elements 29 and 30 OR and the address from register 16 are fed to the inputs of multiplexers 4.1–4.N, and the write signal to

0 inputs of elements 5 I.

The control signals of the outputs of the elements 25 and 26 OR and the address from the counter 27 are fed to the other inputs of the multiplexers 4.1-4.N.

5 The absence of a command synchronization signal from the interface block retains in block 1 the state of the outputs generated from the initial setting signal, which corresponds to the setting for

0 N-oro memory block entries. At the same time, the signal O is set on the N outputs of the decoders 37 and 42, and the signal 1 on the others, which allows connecting the first group of control signals and the address from the Multiple 5 plexor4. M and allowing the recording signal from element 5.N to go to input N of the block memory In this way, the data from control unit 2 is written to the memory unit selected for recording. For

0 of the remaining memory blocks, the other group of control signals and the address from 4.1-4.N-1 multiplexers and the write signal blocking from elements 5.1-5.N-1 remain connected, which corresponds to the installation of blocks

5 memories 6.1-6.N-1 in readout.

Selection block 9 allows the dynamic distribution of layers at the output of the circuit for display on the screen of the indicator.

0 Addressable multiplexers 44.1. 45.1 are the output of register 38.1, and multiplexers 44.N-1, 45.N-1 are output of register 38.N-1.

The information inputs of the multiplexers 44.1-44.N-1 are connected to the corresponding outputs of the shift registers of odd information, and the information inputs of the multiplexers 45.1-45.N-1 to the corresponding outputs of the shift registers of even information. Signals from the outputs

block 9 selection goes to the inputs of block 10, where information is displayed on the display in accordance with the established priority.

In this way, a dynamic redistribution of information between N memory blocks,

Claims (1)

Apparatus of the Invention A device for displaying information on a television indicator screen, comprising a control unit, a group of memory blocks, first and second groups of registers, a selection unit, a video driver and a synchronization unit, the first and second outputs of which are connected to the synchronous inputs of the television indicator, and the third, fourth and fifth outputs - respectively with the clock and first and second gate inputs of the control unit, the first and second outputs of which are connected to the inputs of the register entry, respectively, ne the main and second groups, the information inputs of which are connected respectively to the first and second outputs of the respective memory blocks of the group, and their outputs to the information inputs of the selection unit whose outputs are connected to the information inputs of the imager video signal, the output of which is connected to the video input of the television indicator, and the first gate input - with clock inputs of registers of the first group, the third output of the control unit and the first synchronized input of the selection unit, the second synchronized input of which is connected to the clock inputs of the second group of registers, the second gate input of the video signal generator and the fourth output of the control unit, the fifth output of which is the output of the device response signal, the first and second information and the first control inputs of which are respectively the address input, the information input and the input signal of the block request control, sixth exit which is connected to the information inputs of the memory blocks of the group, characterized in that, in order to increase the speed of the device, it contains the first group of multiplexers, the first the group of elements AND and the control unit of memory, the outputs of the first group of which are connected to the control inputs of the corresponding multiplexers of the first group, and the outputs of the second group to the first the inputs of the corresponding elements AND of the first group, the outputs of which are connected to the recording inputs of the corresponding memory blocks of the group, and the second inputs - with the seventh output of the control unit, the clock and first gate inputs of which are connected respectively to the clock input and the recording input of the memory management unit, outputs the third groups of which are connected to the address inputs of the selection unit, the eighth, ninth and tenth outputs of the control unit are connected to the information inputs of the first group of multiplexers of the first group, first, second and the third outputs of which are connected respectively to the address input and the first and second read inputs of the respective memory blocks of the group, the eleventh, twelfth and thirteenth outputs of the control unit are connected to the information inputs of the second group of multiplexers of the first group, the setup input, the first and second sync inputs and the information input of the block the memory controls are the second, third, and fourth control and third information inputs of the device, respectively. but IZZW.91