TW411537B - Semiconductor package with CSP-BGA structure - Google Patents
Semiconductor package with CSP-BGA structure Download PDFInfo
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- TW411537B TW411537B TW087112600A TW87112600A TW411537B TW 411537 B TW411537 B TW 411537B TW 087112600 A TW087112600 A TW 087112600A TW 87112600 A TW87112600 A TW 87112600A TW 411537 B TW411537 B TW 411537B
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Classifications
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- H—ELECTRICITY
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- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
411537 五、發明説明(1) 發明g诚: 本發明係W於一種半導體封装件,尤指一種得應用 CSP结構於具中央銲墊(Center Bond Pad)晶Η之半導骽封 装件。 背鲁說明: 傳統之引線式半導體装置1為如第U圔所示者•係在 一導線架(Lead FraBe)ll中預黏接雙面膠片110於導脚111 上以將晶片(Die)12黏附至該雙面膠片110上·該晶片12再 藉金線(Gold IHre)13可導電地埋接至Μ晶片12為中心向 外輻射延伸之導»111的内纗111a上,然後將該黏設有晶 片12之辱媒架11置於封裝模具中進行棋壓封装,使封裝睡 通14包覆住該晶片12、金線13及導酈111之内側部分,即 完成半導體裝置1之封裝。該半導臞裝置1在進行去渣/去 结及彎脚成形等作業後*便可裝設至霉子產品所用之印刷 (請先閲讀ί.面之注意事項再填寫本頁) 裝
*1T 出 伸 * 側 對 相 兩 4 IX 艚 膠 装 封 由 其 1Λ置 裝 0導 半。 種 上是 板惟 路 電 蟪 外 之 11 1 1 腳 導 之 間 經濟部中央標準局負工消费合作社印製 置 装« 専 半 該 使 而 離 距 之 , 間外 邊域 側匾 對影 相投 兩之 其14 於髖 大膠 係装 雄封 距之 之ί 域板 區路 翼電 裙刷 之印 成於 形設 影裝 投 1 所置 分趙 伸専 卜半 夕置 1« 11是 腳使 導舍 由遂 一 域 有區 成翼 形裙 再該 會 , 據 佔 會 時 上 無 1 置 裝 導 半 之 鄰 相 兩 使 而 積 面 之 外 額 面 之 板 路 電 刷 印 勢 趨id 計 G 設 —' 之al -小U U、列 置短陣 装、格 發薄柵 導、球 半輕有 種品遂 ~J il 肚產, 用子思 使霣問 令符述 ,K 前 近小決 靠縮解 效法為 有無 法横 1 5640 本纸張尺度適用十國國家標卒(CNS) Λ4規格(210X297公釐) 411537 A7 ___B7_ 五、發明説明(2 ) (請先閲讀尤面之:^意事項再填寫本頁)
Array - BGA)式之半導體裝置問世•一般之BGA半導體装置 2係如第12圖所示者•通常包括在一基板21上黏接有一晶 片22·使該晶片22之上表面設有多数之銲墊23,以在該銲 垫23與敷設於該基板21之上表面211上之第一専電跡線( Electrically Conductive Trace)212間連接金線 24(Wire Bonding) > 其第一導罨跡嬢212係經由開設於基板21上之 貫通孔(vias)213與敷設於基板21下表面214上之第二導霣 跡線215連接;在模壓封装該晶片22*金媒24及基板21上 表面211涵蓋該晶片22與金線24之區域後,則植接銲球(
So丨der Ball)25至蟠接於第二導電跡線215终端之銲墊( Contact Pad)216上*使晶片22得可導電地與該銲球25連 接且通常該銲球係以陣列之型式排列。 經濟部中央標準局員工消资合作社印-象 是種BGA半導髓装置2由於係以整届基板21之下表面 214供銲球25植接* Μ作為I/O之導®,較諸前述半導體裝 置1之導》所能利用的空間僅有封裝膠體之四周邊緣言, 具有較大之利用空間,原因是銲球25係植接於基板21之下 表面214,因而*在基板21之面稹同於前揭半専體裝置1之 封裝膠體14之投影面積時,不會有導腳外伸而產生”佔據 額外空間”之裙»匾域。是Μ,此種BGA半導趙装置2裝設 於印刷電路板上時,即可減少使用面積,亦可緬小印刷電 路板之尺寸·且在使用兩個Μ上之BGA半導體裝置2時*兩 者之間距便可嫌小*而得有效節省使用空間。 然而,是種BG Α半導鼉装置2之金線24係由晶片22之四 周向外輻射K伸接至基板21上表面211上之第一導電跡線 本紙張尺度適用中國國家標啤(CNS ) Λ4規格(2!Ox297公釐) 2 1 5 640 經濟部中央標準局貝工消资合作社印製 411537 at B7五、發明説明(3 ) 212*故在横壓封裝時,封裝膠體26之投影面積須足以涵 蹵金媒24由晶片22向外幅射伸延之區域,而使封装膠體 26之投影面積邐大於晶片22之投影面積*遂令該種BGA半 導裝置之成品尺寸無法進一步縮減,K符現今半導賭裝置 體積縮小化、功能增強化之需求。此外*是種BG A半導體 裝置2之基板21材料昂貴且由於須敷設導霣跡線及開設貫 通孔又難Μ製造•故成本顔高,且因其结構不同於前揭之 半導裝置1·是Μ,並不缠用傳统之封装製程,而需新購 設備,故亦會造成生產成本之增加。 為使BGA半専«裝置能進一步縮減髏積* 一種CSP( Chip Scaling Package)之BGA半導ffi装置遂®運而生。是 種CSP之BGA半専jg装置3大致係如第13圖所示之结嫌*其 特擞在於基板31之投影面樓略大於晶片32之投影面積*故 能使横ffi封装完成後之成品腥積大幅縮小。然而,是種 CSP之BGA半導匾裝置3須使用覆晶(Flip Chip)及錫球凸 塊(Solder Bunping)等先進製造技術·並採用BGA式之基 板,故成本甚高•而只適於高附加價值之高I/O之半導想 元件* g低I/O之半導體元件而言,使用CSP或BGA之结構 製成者,則有製程複雜、成本過高之問題。 為使低I/O之半導體裝置能Μ較低的成本生產出具BGA 结構者•遂有業界人士研發出Μ傳统之導線架為基材的 BGA结構如美國專利5,663,594所椹示者,係Μ傳统模壓方 式進行封裝且利用傳铳之銲線(VireBonding)技術而製成 之具BGA结構之半導髓裝置。參照第14圄,一種具BGA结構 --------¾---------訂------L·-’ — (請先閱讀V面之"意事項再填寫本頁) 本紙張尺度適用國家標华(CNS ) Λ4见格(210X297公釐) 3 1 5 640 4J15S7 at B7 五、發明説明(4 ) 之半導體裝置4係使一晶片42置於導烺架41之導腳412内端 上•藉不導霣膠與専鲫41 2之上表面黏著•並Μ金線4 3分 別銲接至該晶Η 42與導鯽41 2之内蝙上,Κ使晶片42與専 麻412可等霣池接埋;在封装樹腊横壓封裝成一包覆該専 腳412、晶片42及金線43之封裝膠體44時,在相對於各導 »412之下表面之部位係預留有孔洞*俾在封裝膠體44成 肜後*於各孔洞中植接猂球45,Μ使導鼷412可藉_球45 與印刷電路板上之印刷電路可導電地接觸。 是種具BGA结構之半導》装置4雖得顧著地縮減鴉積, 並可利用傳统封装設備與製程,唯此结構僅缠用周进銲墊 (Peripheral Bond Pad),對中央銲蛮(center Bond Pad) 之晶片,仍有製程上的困難,然而為使専》412能有效為 封裝膠體44包覆•位於該専腳412下表面與封裝膠® 44底 面間之厚度即不能太薄*否則便易在固化成形之製程中造 成封裝膠« 44之龜裂,故半導fi裝置無法薄化;同時*由 (請先閱讀背面之A意事項再填寫本頁) 於相 模 於 須 孔 之 通 封 * 壓洞 脚 専 供 可 設 留 中 程 製 裝 與 面 表 下 之 裝 封 注 横 在 故 小 甚 徑 直 之 洞 孔 該 且 時 界 & 旨 汴 fl 樹 經濟部中央標準局員工消費合作社印製 膠 溢 成 形 部 底 之 润 孔 該 於 易 污 會 即 亦 象 現 面 表 下 的 2 11 4 腳 導 之 中 洞 孔 於 霣 外 該 至 染 時 球 植 致 専 而 製 令 as 上 面 表 τ. 的 2 ΊΧ 4 脚専, 至而 接故 銲 。 接佳 直不 法- 無 45品 球成 銲之 , 成 先 後 成 為 而 此 如 率濟會 良予即 完 程 $ 裝 封 壓 横 在 均 者 前 巨 , 仍 而故 然 , , 加 業增 作的 球本 植成 行造 進製 再成 - 造 理並 處化 前雜 之複 洞程 孔製 洗使 濟 予 善 改 待 有 1 5 6 40 本紙沬尺度通用中围國家標準(CNS >A4規格(2丨0X 297公釐) 411537 A7 __B7 _ 五、發明説明(5 ) 基此*本發明之一目的即在提供一種能製程簡單且低 製造成本之具CSP之BGA结檐之半等體封装件。 --------^ ί (請先閲讀Γη面之逢意事項再填寫本頁) 本發明之另一目的在提供一棰能有效薄化厚度而符合 薄彤半専趙產品之需求的具CSP之BGA结構之半専體封裝件 0 本發明之再一目的在提供一種能以傳统之封裝設備及 製程製成且遘用於中央銲墊晶片之具CSP之BG A结構的半専 ®封装件。 本發明之又一目的在提供一種無須使用BGA式之基板 而可直接使用専線架為基材的具CSP之BGA結構之半導想封 装件。 依據本發明上揭目的提供之具CSP之BGA结構的半導體 封装件•係包括: 一具有中間纓空區之至少二俩上開設有多数圼柵格陣 列之孔洞之不導電基曆(Non-conductive Base Layer), 該基層具有相對之第一表面與第二表面; 經濟部中央標準局員工消费合作社印製 接著於該基靥之第二表面上之専線架之専脚,使該専 脚之内皤伸露該基靥之鏤空區中且均彼此分隔,該導酺具 有相對之上表面與下表面,並令各導躑上表面均對懕於基 層之孔洞; 、 一黏設於各導酈下表面上之晶片,該晶片具有頂面與 底面; 多數連接於晶片頂面與各導脚内纗上表面上之捍線· 以使該晶片與導鯽可導電地接連; 本纸乐尺度適用中國國家標率(CNS ) Α4規格(210X297公釐} 5 1 5 6 40 經濟部中央標準局貝工消費合作ii印製 411537 A7 __B7_五、發明説明(6 ) 包覆該晶片,銲媒及導腳未黏接著有基蘑之部分的封 裝膠體•使該基餍大致外兹出該封裝膠體;κ及 多數植接於該基層之孔洞中並外露出該孔洞之銲球· μ使該銲球可導電地連接至該導腳之上表面。 於本發明之另一實施例中•該封装膠體得於固化成形 後,使晶片之底面外露出封裝膠體而成裸晶之型式。 於本發明之又一實施例中,該導脚之外端部分係可外 荛出該封裝膠體·κ使至少南俚本發明之半導體封装件得 上下叠置,令位於上方之半専髓封装件之銲球得觸接至位 於下方之半導體封裝件之導®之外»部分,而令彼此可導 霉地相接。 本發明所稱之基層係為如聚亞醢胺樹脂製成之不導霣 膠片(Tape)或如環氧樹脂製成之不専電拒銲劑(Solder Mask) *故使用除片為基β時,僳以鈷貼之方式使膠Η與 導線架之専黼接著,而在使用担銲劑為基層時,則係以塗 佈之方式使拒銲覿與導線架之導鼸接著。 _式筋盟說明 第1圖係本發明第一實施例具CSP之BGA结構之半導體 封裝件剖面示意匾; 第2醒係本發明第一霣施例具CSP之,BGA结構之半導體 封裝件所使用之導線架的俯視圈; 第3國係本發明第一 S豳例具CSP之BGA结構之半導體 封裝件所使用之基片的俯視画; 第4Β係本發明第一實腌例具CSP之BGA结構之半専體 本紙乐尺度適用中國_家標率(〔:ns ) Λ4規格(2i〇x297公釐) 6 1—5 6 4 0 I J- . In . . i ϊ - xi衣 .i - 1-- - I - ' 1-- - I (請先閲请背面之注意事項再填寫本I ) 411537 A7 經濟部中夾標窣局員工消費合作社印31 __B7_五、發明説明(7 ) 封裝件使用之導線架與基片黏结後之俯視圖; 第5圖係本發明第一簧施例具CSP之BGA结構之半導體 封裝件將晶片黏設於已黏貼有基片之導線架上的剖面示意 國 * 第6_係第5圓之结構置於封裝横具中之剖面示意圈; 第7圏係第5謹之结構完成封装及植球並進行去邊之動 作示意圈; 第8·係本發明第二實施例具CSP之BGA结構之半導S 封装件的剖面示意圔; 第9圓係本發明第三實施例具CSP之BGA结構之半導膛 封裝件的剖面示意匾; 第10蘭本發明第三實施例具CSP之BGA结構之半導體封 裝件或三届上下叠置之剖面示意画; 第U画係習知引線式半導體裝置之剖面示意圖; 第12圈係習知BGA半導體裝置之剖面示意豳; 第13圖係習知CSP之BGA半導想装置之剖面示意園; Μ及 第14臛係習知之Μ導線架為基材之BGA结構之半導體 装置之剖面示意匾。 , 本發明第一實施例之具CSP结構之半専體封裝件5,如 第1至3圓所示,係包括基片51(亦可使用担銲劑)·黏設於 基Η51上之多數導鬭52*黏接至該専脚52下表面524之晶 片53·可導霣地連接晶片53與導Η52内端部521上之金線 (請先閱讀.背面之注意事項再填寫本頁) 裝 。丁 •-β ^-丨 本纸張尺度適用中國國家標哗((:NS ) ΛΊ現格(210Χ297公釐> 1 5640 經濟部中央標隼局負工消費合作社印製 A7__411537_b7__五、發明説明(8 ) 54·包覆該晶片53、金線54及導»52之封装應體55,K及 植接至該基片51上開設之多數圼柵格陣列之孔洞511中之 銲球5 6。 如第1及2圔所示,該由銅合金或鐵鎳合金製成之導脚 52係以其外通部522端連至一矩形裙片(Skirt Strip)523 上而成一導媒架(LeadFraBe)50;各該導脚52並具有下表 面5 2 4及上表面5 2 5。 如第1及3鼷所示,該基片51則為如聚亞醢胺樹腊之附 高溫高分子材料製成者*係於中間位置形成有一鏤空區 512,使各孔润511係呈檷格陣列的開設於該鏤空區512長 度方向之兩铟上,並具有第二表面513及第一表面514。 該銲球56植接於各孔洞5U中時偽彤成一黏接至導腳 52上表面525上之根部561及一外露出該孔洞511润緣之球 部 56 2。 該具CSP之BGA结構之半導髖封装件5之製程•係先將 基片黏於導脚之上表面525上,並使各専脚52之内端部521 係伸霣該基片51之鏤空¥512中•且使各孔洞511均對應於 各導臟52之上表面525*即如第4_所示者,各導麻52之上 表面525為基片51所蓋覆區域均有栢對於該孔洞511之部分 經由孔润511露出至外界。在専脚52的下表面524上黏著一 習用接著雙面鏐著片57後*即可將晶片53黏接至該接著片 57上,而使晶片53得Μ専鼸52為支撐並黏固於等脚52上· 如第5圈所示。晶Η53與導»52内通部521黏著亦可以習知 之不導霣銀膠為之。 ^1^1 ^·ϋι -- -Id u_3_ --a (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用t國國家標準(CNS )A4規格(2丨0X 297公釐) 8 1 5640 經濟部中央標準局負工消贽合作社印焚 411537 g五、發明説明(9 ) 接而,將金線54之一端連接至設於晶片53之頂面531 上之銲墊(未圖示),而另一竭則蟠接至導脚52位於內编部 521之上表面525上的缠當處,以使晶片53可専電地與専肠 52接連。完成後*如第6鼴所示,即可將之置於封裝模具 58中進行携颳。棋壓完成後•固化成型之封裝膠體55即包 覆住該晶片53、金媒54及専酈52未黏接有基片51之部分; 由於封裝膠S55不包覆住基片51設有孔洞511之部位*亦 , 即於灌注封装樹胞時,横流並不流經孔洞511,因而模壓 完成至封裝膠髓55固化成形後•孔洞511中仍保持潔淨, 不致有為封装樹脂污染之問鼸;是以*在封裝膠想55固化 成形後•印可立即進行植球作業•如第7圖所示,將_球 56植人各該孔洞511中* K使導鼷52與諄球56可導電地連 接,並在進行去渣/去邊作業K將導》52輿裙片523分離, 即完成本發明之具CSP结構之半専體封装件5。此外*該半 導體封装件5之封裝謬《55的投影面積偽不大於晶片53面 積之1 . 2倍。 本發明之具CSP之BG A结構之半専體封裝件5製成後* 即可装設於印刷霄路板上並藉著銲球56可導電與印刷電路 板職结。作為I/O之銲球56係列設於該半導》封装件5之底 面上,故有BGA结構之功效•然卻又不同於習用BGA基板須 於上、下甬表面上敷設導霣跡線及貫通孔之方式*故使用 傳統之導酈架構、_嬢方式及模S製程即可•而使本發明 具CSP之BG A结構之半導暖封裝件5的製造成本甚低。同時 ,該Μ基片51與導»52黏接之方式·能免除封裝暖SI55對 (請先閲讀背面之注意事項再填寫本f ) 裝 ,-- 本紙張尺度適用中國國家標準(CNS ) A4規格(2I0X297公釐) 9 1 5640 411537 A7 B7五、發明説明(10) 専脚52上表面525之盖覆,因而,使用厚度不大於200微米 (200um)且不會產生龜裂現象之砍性基片51,能使本發明 之具CSP之BGA結構之半導81封裝件5符合薄型半専體產品 之需求。再者*本發明於摸壓封裝之過程中,封裝樹脂之 棋流不舍流經基H51設有孔洞511之部位*故孔洞5U在横 颳作業完成後•不會受到封装樹脂的污染*也沒有溢滘之 規象*故不用如習知之具以導媒架為基材之BGA结構之半 導通裝置在横壓完成後須先對孔洞進行淸洗之前處理· Μ 去除封装樹脂之污染或溢膠之問謳•方得進行植球作業; 亦即·本發明在横颳完成後*便得直接進行植球作業•故 可簡化製程並降低製埴成本。 如第8圖所示,係本發明之第二實施例。該第二霣施 例所示之具CSP之BGA结構之半導體封装件5’大致同於第一 實施例中所堪示者•惟在横壓完成後,固化成形之封裝膠 «55'並未Μ覆住晶片53’之底面532’·亦即,晶片53’之 底面532’係裸S出封裝膠》55·而直接與大氣接觸;此種 裸晶式之封装方法可提供製成之具CSP之BGA结構之半専Β 封裝件5’具有較佳之敗熱效果|因晶片53’於導霄後產生 之热1得以直接散逸至大氣中。 如第9圓所示者為本發明之第三實施例。該第三實施 例所示之具CSP之BGA结構之半導體封裝5”係大致同於第一 賁腌例所揭示者,其不同處在於本寘狍例之専腳52"之外 蠼下表面522 "並未為封装膠《855 "MS ·而汰外两出封裝 除體55”。此種结構可供兩個K上之半導賊裝置上下«置 本紙伕尺度诚用中闺囤家標't ( ('NS ) Λ视格(2ΙΟΌ7公犛) ~ ΓΤΤ7Τ 10 15640 (請先閱讀背面之注意事項再填艿本頁) —m^i ^^^^1 In ^ 1 一laJ^ilff ^^^^1 ^ip. 411537 Α7 Β7 i'f.4部中决榡卑扃只工消资合5r.iL印ΐί 五、發明説明(u) ,如第lOffl所示|具CSP之BGA結構之半導臢封裝件5A"、 5&”及5C”依序上下叠接•使位於中間之半専體封裝件5B” 底面上之銲球56B"得觸接至•半専封裝件5A"之外露出封 裝膝體的外端部522A”上,同理*半導髖封裝件5C”底面上 之銲球56” C得觸接至半導體封装件5B”之外兹出封裝膠體 的外嬙部522B"上,依此方式II置後,半導髖封裝件5A”、 5B”及5C”即得可専«地職结。此外,第三例之半導» 封装件5”亦可採用第三實施例中所揭示之裸晶型式者。 以上所述者·僅為用以例釋本發明之特點及效果,而 非用以限定本發明之可實施範圍,其他未脫離本發明所揭 示之精神與原理下所完成之等效改變或修飾,如鏤空區之 形狀得為矩形、檷®形或多角形等*均應包含於下述之専 利範圃内。 符狨銳明 1 引媒式半導《装置 2 BGA半導體装置 3 CSP之BGA半導if装置 4 習知具導線架為基材之BGA结構之半導體裝置 5 ' 5、5 " 5 A ”、5 B ”、5 C ” 具C S P之B G A結構之半導體封裝件 11 導線架 1 2 晶片 1 3 金腺 14 封裝膠» (請先閱讀肯面之注意事項再填艿本頁) 裝
rlT 本紙张尺度適川中國S家棉( rNS M4現格(2!〇Χ 公萆) 11 1 5 6 4 0 411537 A7 B7 五 '發明説明(12) 21 基 板 2 2 晶 片 23 m 墊 24 金 線 25 η 球 26 封 裝 膠 69 31 基 板 32 晶 片 41 導 媒 架 42 晶 片 43 金 媒 44 封 裝 膠 « 45 嬅 球 50 導 線 架 5 1 基 片 52 ^ 52 導臛 53 > 53 t 晶Μ 54 金 線 5 5' 55 ' 、55 封 裝 膠Η 56 ' 58 Β " 1 > 56 C" 捍 球 57 接 著 雙 面膠 Η 58 封 装 播 具 1 10 接 著 赞 面謬 Η 111 導腳 (請先閱讀背面之;i意事項再填艿本頁) ¾ 订 本紙乐尺度迖川中阁囤家標肀((’NS ) Λ4規格(2丨0:<297公犛) 12 1 5 6 4 0 411537 A7 B7 五、發明説明(13) 111a 内端 111b 外端 21 1 上表面 212 第一導電跡線 213 貫通孔 214 下表面 215 第二専霣跡媒 216 銲墊 412 導腳 511 孔洞 512 鏤空區 514 第一表面 513 第二表面 521 内端部 522、 522"、 522A” 522B"外锄部 523 裙片 52 4 下表面 5 2 5 上表面 531 頂面 5 3 2 ’底面 561 根部 5 6 2 球部 (請先閱讀背面之注意事項再填巧本頁) 焚 訂 本紙沬尺度消州中闽因家標肀(('MS ) Λ4坭格(;ΜΟχ Μ?公f ) 1 3 1 5640
Claims (1)
- 申請專利範圍修正本 (89年5月25日) 1. 一種具CSP結構之半導體封裝件,係包括: 一具有鏤空區並於該鏤空區之至少二側上開設有 多數呈柵狀陣列孔洞之基層,使該基層具有相對之第 一表面與第二表面; 多數接著至該基層之第二表面上之等腳,使該導 腳之内端伸露於該基層之鏤空區中且均彼此分隔,該導 腳具有相對之上表面與下表面,並令各導腳之上表面均 對應於該基層之孔洞; 片 晶 該 使 片 晶 之 上 面 表 下 端 ., 内面 腳底 導與 各面 於頂 設之 黏對 1 相 有 具 之 上 面 表 上 端 内連 腳接 導地 各電 與専 面可 頂腳 Η 導 晶 與 該片 於 晶 接該 連使 數 Μ 多 -線 銲 及位 分部 郜之 之洞 層孔 基有 有設 著開 接層 未基 腳該 導使 及 , 線體 銲膠 、 裝 Η 封 晶的 該區 覆空 包鏤 層 基 經濟部中央標準局員工福利委貝會印製 球 銲 之 洞 孔 該 出 露 外 並 中 洞 及孔 Μ層 ; 基 體該 膠於 裝接 封植 該數 出多 露 外 基 該 ο I 面中 表其 上 * 之件 腳裝。 専封者 該體成 至導製 接半料 埋之材 地項溫 電 1 高 導第耐 可圍之 球範電 _ 利専 該專不 使請W 以申係 , 如 層 2 層 基 該 中 其 件 裝 封 體 導 半 之 。 項者 2 成 第製 圍脂 範樹 利胺 專醢 請亞 申聚 如係 3 層 基 該 中 其 件 裝 封 體 導 半 之 項 1 第 圍 範 利 專 請 ¢ 如 本紙張尺度適用中a國家標準(CNS )A4規格C 210 X 297公金) 1 1 5 6 40申請專利範圍修正本 (89年5月25日) 1. 一種具CSP結構之半導體封裝件,係包括: 一具有鏤空區並於該鏤空區之至少二側上開設有 多數呈柵狀陣列孔洞之基層,使該基層具有相對之第 一表面與第二表面; 多數接著至該基層之第二表面上之等腳,使該導 腳之内端伸露於該基層之鏤空區中且均彼此分隔,該導 腳具有相對之上表面與下表面,並令各導腳之上表面均 對應於該基層之孔洞; 片 晶 該 使 片 晶 之 上 面 表 下 端 ., 内面 腳底 導與 各面 於頂 設之 黏對 1 相 有 具 之 上 面 表 上 端 内連 腳接 導地 各電 與専 面可 頂腳 Η 導 晶 與 該片 於 晶 接該 連使 數 Μ 多 -線 銲 及位 分部 郜之 之洞 層孔 基有 有設 著開 接層 未基 腳該 導使 及 , 線體 銲膠 、 裝 Η 封 晶的 該區 覆空 包鏤 層 基 經濟部中央標準局員工福利委貝會印製 球 銲 之 洞 孔 該 出 露 外 並 中 洞 及孔 Μ層 ; 基 體該 膠於 裝接 封植 該數 出多 露 外 基 該 ο I 面中 表其 上 * 之件 腳裝。 専封者 該體成 至導製 接半料 埋之材 地項溫 電 1 高 導第耐 可圍之 球範電 _ 利専 該專不 使請W 以申係 , 如 層 2 層 基 該 中 其 件 裝 封 體 導 半 之 。 項者 2 成 第製 圍脂 範樹 利胺 專醢 請亞 申聚 如係 3 層 基 該 中 其 件 裝 封 體 導 半 之 項 1 第 圍 範 利 專 請 ¢ 如 本紙張尺度適用中a國家標準(CNS )A4規格C 210 X 297公金) 1 1 5 6 40本紙張尺度適用中a國家標準(CNS )A4規格(210X 297公漦) 2 1 5 6 40本紙張尺度適用中a國家標準(CNS )A4規格(210X 297公漦) 2 1 5 6 40 411537 H3經濟部中央標準局員工福利委員會印製 .V舉V表面與第二表面; 多數接著至該基層之第二表面上之専腳,使該専 脚之內端伸II於該基層之鏤空區中且均彼此分隔,該 専腳具有相對之上表面與下表面•並令各導腳之上表 面均對應於該基層上之孔洞; 一黏設於各導腳内端下表面上之晶片,使該晶片 具有相對之頂面與底面; 多数連接於該晶Η頂面與各導腳內端上表面上之 銲線·Κ使該晶片與導脚可導電地接連; 包覆該晶片、捍線、導脚未接著有基片層部分及 基層鏤空區的封裝膠體,使該基層開設有孔洞之部位 以及該導腳外端部之下表面分別外兹出該封裝膠體; 及 Μ 球 有 銲 設 之 。 : 開 洞 面括上 孔 表包側 該下係二 出之 ,少 露腳件至 外導裝之 並 該封區 中 至體空 洞接導鏤 孔 連半該 層地 之於 基 電構並 該導结區 於可GA空 接球_Β鏤 之 植銲 Ρ 有 數該CS具 多 使具一 -is 知 種 之 導該表 片 對 該 ,上 晶 相 使隔之 該 有 ,分腳 使 具 腳此導 _ 層 導彼各 片 基 之均令 晶 該 上且並 之 使 面 中 * 上 * 表區面 面 層 二空表,,表 基 第鏤下洞下 之 之之 與孔端 洞;層層面之内 孔 面基基 表上腳 之 表該該上層導 列 二至於 之基各 陣 第著露 對該於 吠與接伸相於設 柵面數端有應粘 圼表多 内具對 一 數一 之脚均 多第 腳導面 面 底 與 面 頂 之 對 相 有 具 本紙張尺度適用中國國家標準(CN S) A4規格(210 X 297公金) 1 5640 411537 H3經濟部中央標準局員工福利委員會印製 .V舉V表面與第二表面; 多數接著至該基層之第二表面上之専腳,使該専 脚之內端伸II於該基層之鏤空區中且均彼此分隔,該 専腳具有相對之上表面與下表面•並令各導腳之上表 面均對應於該基層上之孔洞; 一黏設於各導腳内端下表面上之晶片,使該晶片 具有相對之頂面與底面; 多数連接於該晶Η頂面與各導腳內端上表面上之 銲線·Κ使該晶片與導脚可導電地接連; 包覆該晶片、捍線、導脚未接著有基片層部分及 基層鏤空區的封裝膠體,使該基層開設有孔洞之部位 以及該導腳外端部之下表面分別外兹出該封裝膠體; 及 Μ 球 有 銲 設 之 。 : 開 洞 面括上 孔 表包側 該下係二 出之 ,少 露腳件至 外導裝之 並 該封區 中 至體空 洞接導鏤 孔 連半該 層地 之於 基 電構並 該導结區 於可GA空 接球_Β鏤 之 植銲 Ρ 有 數該CS具 多 使具一 -is 知 種 之 導該表 片 對 該 ,上 晶 相 使隔之 該 有 ,分腳 使 具 腳此導 _ 層 導彼各 片 基 之均令 晶 該 上且並 之 使 面 中 * 上 * 表區面 面 層 二空表,,表 基 第鏤下洞下 之 之之 與孔端 洞;層層面之内 孔 面基基 表上腳 之 表該該上層導 列 二至於 之基各 陣 第著露 對該於 吠與接伸相於設 柵面數端有應粘 圼表多 内具對 一 數一 之脚均 多第 腳導面 面 底 與 面 頂 之 對 相 有 具 本紙張尺度適用中國國家標準(CN S) A4規格(210 X 297公金) 1 5640本紙張尺度適用中a a家標準(CNS )A4規格(210 χ 297公董) 4 1 5 6 4 0本紙張尺度適用中a a家標準(CNS )A4規格(210 χ 297公董) 4 1 5 6 4 0
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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TW087112600A TW411537B (en) | 1998-07-31 | 1998-07-31 | Semiconductor package with CSP-BGA structure |
JP35582598A JP3155741B2 (ja) | 1998-07-31 | 1998-12-15 | Cspのbga構造を備えた半導体パッケージ |
US09/235,095 US6528722B2 (en) | 1998-07-31 | 1999-01-21 | Ball grid array semiconductor package with exposed base layer |
Applications Claiming Priority (1)
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TW087112600A TW411537B (en) | 1998-07-31 | 1998-07-31 | Semiconductor package with CSP-BGA structure |
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TW411537B true TW411537B (en) | 2000-11-11 |
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TW087112600A TW411537B (en) | 1998-07-31 | 1998-07-31 | Semiconductor package with CSP-BGA structure |
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JP (1) | JP3155741B2 (zh) |
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Cited By (2)
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Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6949824B1 (en) * | 2000-04-12 | 2005-09-27 | Micron Technology, Inc. | Internal package heat dissipator |
US6762502B1 (en) * | 2000-08-31 | 2004-07-13 | Micron Technology, Inc. | Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof |
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US8278751B2 (en) * | 2005-02-08 | 2012-10-02 | Micron Technology, Inc. | Methods of adhering microfeature workpieces, including a chip, to a support member |
US7851896B2 (en) * | 2005-07-14 | 2010-12-14 | Chipmos Technologies Inc. | Quad flat non-leaded chip package |
US20080315417A1 (en) * | 2005-07-14 | 2008-12-25 | Chipmos Technologies Inc. | Chip package |
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US7485502B2 (en) * | 2006-01-31 | 2009-02-03 | Stats Chippac Ltd. | Integrated circuit underfill package system |
US20070241441A1 (en) * | 2006-04-17 | 2007-10-18 | Stats Chippac Ltd. | Multichip package system |
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US8169067B2 (en) | 2006-10-20 | 2012-05-01 | Broadcom Corporation | Low profile ball grid array (BGA) package with exposed die and method of making same |
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JP6052235B2 (ja) * | 2014-05-27 | 2016-12-27 | トヨタ自動車株式会社 | 歩行訓練装置 |
JP6052234B2 (ja) * | 2014-05-27 | 2016-12-27 | トヨタ自動車株式会社 | 歩行訓練装置 |
KR200483467Y1 (ko) * | 2015-10-28 | 2017-05-18 | 방부현 | 편마비 환자용 보행보조기구 |
WO2017077837A1 (ja) * | 2015-11-05 | 2017-05-11 | 株式会社村田製作所 | 部品実装基板 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268101A (ja) * | 1993-03-17 | 1994-09-22 | Hitachi Ltd | 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板 |
JP2780649B2 (ja) * | 1994-09-30 | 1998-07-30 | 日本電気株式会社 | 半導体装置 |
JP3793628B2 (ja) * | 1997-01-20 | 2006-07-05 | 沖電気工業株式会社 | 樹脂封止型半導体装置 |
US6020637A (en) * | 1997-05-07 | 2000-02-01 | Signetics Kp Co., Ltd. | Ball grid array semiconductor package |
JP3611948B2 (ja) * | 1997-05-16 | 2005-01-19 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置及びその製造方法 |
US5952611A (en) * | 1997-12-19 | 1999-09-14 | Texas Instruments Incorporated | Flexible pin location integrated circuit package |
US6072233A (en) * | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
JP2000138262A (ja) * | 1998-10-31 | 2000-05-16 | Anam Semiconductor Inc | チップスケ―ル半導体パッケ―ジ及びその製造方法 |
US6150730A (en) * | 1999-07-08 | 2000-11-21 | Advanced Semiconductor Engineering, Inc. | Chip-scale semiconductor package |
US6326700B1 (en) * | 2000-08-15 | 2001-12-04 | United Test Center, Inc. | Low profile semiconductor package and process for making the same |
-
1998
- 1998-07-31 TW TW087112600A patent/TW411537B/zh not_active IP Right Cessation
- 1998-12-15 JP JP35582598A patent/JP3155741B2/ja not_active Expired - Fee Related
-
1999
- 1999-01-21 US US09/235,095 patent/US6528722B2/en not_active Expired - Lifetime
Cited By (3)
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US6821876B2 (en) | 2002-09-10 | 2004-11-23 | Siliconware Precision Industries Co., Ltd. | Fabrication method of strengthening flip-chip solder bumps |
CN104617088A (zh) * | 2013-11-05 | 2015-05-13 | 矽品精密工业股份有限公司 | 半导体封装件及其制法与基板暨封装结构 |
CN104617088B (zh) * | 2013-11-05 | 2018-01-30 | 矽品精密工业股份有限公司 | 半导体封装件的制法 |
Also Published As
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US6528722B2 (en) | 2003-03-04 |
JP3155741B2 (ja) | 2001-04-16 |
JP2000058711A (ja) | 2000-02-25 |
US20020046854A1 (en) | 2002-04-25 |
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