TW457662B - Fabrication method and structure of a chip size package - Google Patents

Abstract

A fabrication method of a chip size package comprises: providing a chip in which the top side of each chip has a plurality of bonding pads; providing a metal plate in which the metal plate is divided into an upper layer and a lower layer, and forming at least a placement region corresponding to at least an aforementioned chip on the surface of the upper layer in the metal plate; partially etching the upper layer of the metal plate to form a plurality of redistributed conductive lines in which the conductive lines are supported by the lower layer of the metal plate; joining the chip into the placement region on the upper layer of the metal plate, and electrically connecting to the conductive lines; providing a bottom pad between the chip and the upper layer of the metal plate; and removing the lower layer of the metal plate such that the present invention has the function of connecting with multiple pins and has a smaller thickness.

Description

89122018 4 ΤΤΤ6 " ι. Description of the invention [Field of the invention] The present invention relates to a method for manufacturing a chip size package (CSP), and particularly to a type of substrate that is free of use and has redistribution. Manufacturing method of chip size package. [Previous technology] Chip Size Package (CSP) is a general term for packages with the same or slightly larger chip size, which meets the current requirements for thin electronic components, and is compatible with bare chips. ] And flip-chip [f 1 ip ch ip] has better protection of the wafer to resist dust and moisture. Generally, the chip size package structure has an interposer structure between the wafer and the solder bumps. The interposer can be used for a substrate or lead frame where the substrate has the disadvantages of thicker package thickness and higher cost. The lead frame has a poor contact redistribution effect and cannot be used to package a multi-terminal chip. For example, US Patent No. 5, 894, 107 discloses a chip size packaging structure using two lead frames. One lead frame provides pins that are combined with the chip and the second lead frame provides bumps that are electrically connected to the outside. The pin positioning of the first lead frame uses a dam tar on the periphery to fix the pins. Insufficient flexibility can easily shift and the shape of the pins is restricted to achieve the best redistribution effect. Or, for example, a method for manufacturing a wafer-size package of the United States Patent No. 5, 951, 8 04 ’is to use a TAB tape [Tape Automated

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Bonding, tape-and-tape automatic bonding] affixed to the bottom surface of a lead frame strip, and after bonding the wafer with TAB tape, it is sealed with TAB tape to obtain a csp packaging structure, in which pins are formed on the TAB tape, and the pins are A polyimide tape must be affixed to the wafer and sealed at multiple locations. Not only is the TAB tape difficult and costly to form, but it is also formed in the CSP package structure to effectively reduce the thickness. ~ ^ [Objective of the invention] The main purpose of the present invention is to provide a method for manufacturing a wafer size package, which uses a partial etching method to form a redistribution conductive circuit on a metal plate, so that a wafer having a general pad distribution can be used for the wafer. Size package structure. A second object of the present invention is to provide a method for manufacturing a wafer-size package, which uses a partial etching method to form a redistribution conductive line on a metal plate, so that a wafer-size package structure with multiple terminals can be manufactured. / Another object of the present invention is to provide a chip-size package structure, wherein the conductive circuit used for redistribution in the chip-size package structure is divided into ^: Don't be under a metal plate in the manufacturing process and after sealing It is fixed by the sealant and body of the bottom pad. Therefore, it has the thinnest thickness without the use of a substrate and can provide the best dispersion of the external electrical connection point distribution, improving the chip size. The surface of the packaging structure is bonded to the circuit board [SMT] on the circuit board. The yield. According to the method for manufacturing a wafer size package according to the present invention, the steps include: providing at least one wafer, wherein a plurality of solder pads are provided on the front surface of each wafer;

Page 6 457662 V. Description of the invention (3)-Provide a metal plate, wherein the metal plate is divided into an upper layer and a lower layer, and at least one surface corresponding to the above crystal area is formed on the surface of the upper layer of the metal plate; The surname is engraved on the upper layer of the metal plate to form a plurality of redistributed lines, and the plurality of conductive lines are carried by the lower layer of the metal plate = each has a first end point and a second end point of $ One end point corresponds to the welding pad of the wafer and the second end point is dispersed in the placement area; and, the placement area of the Ba sheet above the metal plate, and the first pad of the wafer and the first conductive line The end point; connecting the front side of the wafer and the surface of the upper layer of the metal plate; and removing the lower layer of the metal plate. [Detailed description of the invention] Please refer to the attached drawings to illustrate the present invention by the following embodiments: The method for manufacturing a chip size package according to the first embodiment of the present invention includes the following steps. As shown in FIG. 1, at least one wafer 11 is provided, wherein a top surface of the wafer 110 is provided with a plurality of pads 1 Π, and the wafer 11 {} is a conventional type. The wafer form 'its pads 111 are close to the four perimeters on the front face of the wafer and are closely spaced together, which can be used to wire and bond to adjacent pins or substrates in the conventional packaging process. Pads 丨 丨 can be formed with conductive bumps 112 [bump] and become a chip in the form of flip chip [n ip chip] [as shown in the third figure], in general, the wafer 1 1 0 of pads 11 1 pitch [pitch] extremely small [about 4 〇 ~ 1 〇〇 #

Page 7 5 7 6 6 2 V. Description of the invention (4) "-m 1 'for bonding wires or bumps in a package structure, because the distance between the surface bonds is too small, it is not suitable for direct flip chip bonding On the circuit board. As shown in FIG. 2 'providing] a metal plate 120, wherein the metal plate is divided into an upper layer 121 and a lower layer 122 [please refer to FIG. 3a]' forming at least one correspondence on the surface of the upper layer 121 of the metal plate In the above-mentioned placement area 126 of the wafer Π0, the metal plate 120 may be a copper foil layer, which is provided as a lead frame of the wafer-size package structure of the wafer Ji. As shown in Figs. 2 and 3a, partly etching the upper layer 121 of the metal plate 120 to form a plurality of redistribution conductive lines 123, and the plurality of conductive lines 123 are formed by the metal plate. It is carried by the lower layer 122 of the 120, that is, the conductive line 123 is raised above the lower layer 122 of the metal plate and is `` supported '' so that the upper layer 121 of the warehouse plate 120 is named. Only the conductive line 123 is left 'wherein the conductive line 123 is not of equal length and has any desired curved shape' The formation of the conductive line 123 can be performed by conventional techniques, such as masking the metal with a mask The conductive lines 1 2 3 on the surface of the upper layer 121 of the board 120 are obtained by applying a part of the time. At the same time, the plurality of conductive lines 1 23 each have a first terminal 24 and a second terminal 25. The first end point 1 2 4 is corresponding to the pad π of the wafer π and is close to the four perimeters of the placement area 126 to serve as an internal electrical connection with the pad 1U of the wafer 110 and the second end point. 125 series are dispersed in the placement area 126 for the wafer ruler External electrical connection of the package, and since the first end adjacent the second end 125 than adjacent the point 124 has a more uniform dispersion of the distribution, it is

457662 V. Description of the invention (5) The second end point 125 of the conductive line 123 is used as a redistribution arrangement of the external electrical connection point of the chip 11, and in addition, the conductive line 2 3 can also be regarded as a [1 ead finger] of the lead frame of the chip size package structure. As shown in FIG. 3a, 'securing] the above-mentioned wafer 110 to the placement area 126 of the upper layer 12m of the metal plate 120, and the bumps 112 [bump] are electrically connected to the pads 11 1 of the wafer 11 and the conductive lines 1 2 The first end point of 3 is 1 2 4 as shown in Fig. 3a. 'Since the pad ui of the wafer 11 is located close to the four perimeters of the front face of the wafer II 0, the conductive line 2 3 should be matched with the corresponding pad. III 'The direction of its first end point 1 24 to the second end point 1 25 is extended from outside to inside or long or short and the second end point 125 is evenly dispersed in the placement area 126. In addition, the wafer 11 The electrical connection between the solder pad 1 1 1 of 0 and the first terminal 1 24 of the conductive line 1 2 3 is a bump 丨 〖2, so that the wafer in a crystalline form 丨 i 〇 is re-soldered [re-fi 〇w] and other methods are combined with the placement area 126 of the upper layer 12m of the metal plate 120. When combined, the plurality of conductive lines 123 are integrally carried by the lower layer 122 of the metal plate 120 without any displacement. Conditions, or even the phenomenon of shedding, is far more than the conventional lead frame using a dam bar on the outer periphery to connect the fixed pins It is stable, and the conductive line 123 can have any desired length and curved path. At the same time, in order to reduce the stress caused by the difference in thermal expansion coefficient between the wafer 110 and the conductive line 123, the front surface of the wafer 110 and the layer 121 above the metal plate 120 An underfill 130 [underfill] is provided therebetween, wherein the underpad 13 can be a liquid epoxy compound with thermosetting liquid or other, and the forming step can be performed at the same time as the bonding pad for rebonding the wafer 110 at the same time.丨 ^ and

457662

The step of the first terminal i24 of the conductive circuit 123 is completed to serve as the encapsulation of the front surface of the wafer 110 and the surface of the upper layer 121 of the metal plate 120. As shown in FIG. 3b, the etching is finally performed. [EtcMng] or grinding [grinding] and other methods to remove [removering] the metal plate 丨 2 lower layer 1 22 'to obtain at least one wafer size package junction size package structure-wafer 11G, its bottom surface [ie the front side ] = = Several pads 111, and bumps are formed on the plurality of pads〗 12;, a plurality of redistributed conductive lines 123 ′, and the plurality of conductive lines 123 are formed and uniformly formed by the y mountain metal plate 120 There are connected first end points 124 and second / end points 125, wherein the first end point 124 is bonded to the pad pads of the wafer by the bump η, and the second end point 125 is distributed corresponding to the wafer 11 ( ) Bottom Γ lit bottom 塾 130 'It is located between the bottom surface of the chip 110 and the plurality of conductive lines 123 to become the sealing compound (packa 讧) of the package structure. The above-mentioned chip size package structure can also be at the second endpoint 125 seed solder balls or conductive adhesive [c〇nduc tive] for combination with a circuit board (not shown in the drawing), because &, the chip size packaging structure according to the present invention has the thinnest thickness due to the use of a free substrate, and uses the conductive properties of the multiple heavy knives The circuit 1 2 3 can provide the best distributed external electrical connection point distribution, and improve the bonding yield of the chip size package structure on the circuit board surface. In addition, the above-mentioned conductive circuit 123 can be regarded as a lead finger of a lead frame. Obviously, the manufacturing method of the chip size package of the present invention has the following effects: First, the redistributed conductive lines formed by the partial etching method

Page ί 57 ^ 57662 V. Description of the invention (7) The 1 2 3 series is integrally fixed and carried by a metal plate 丨 2 〇 under the layer i 2 2 at the bottom so as to electrically combine the chip 丨 丨 and the conductive circuit丨 2 3, the conductive line 123 does not shift and has the function of accurate internal electrical connection; second, the conductive line 123 is fixed by the lower layer 122 of the metal plate 120 during the manufacturing process and the metal plate 12 is removed 〇 The lower layer 122 is attached and fixed by the bottom pad 130 and the bump 112, so it has a relatively thin thickness without using a substrate; third, because it is a more dispersed second endpoint of the conductive line 1 2 3 1 2 5 As the redistribution of external electrical connection points of the chip 1 10 to increase the distance between adjacent external contacts within a limited area, it has the effect of improving the correct combination with the surface of the circuit board. The method of manufacturing a wafer size package according to the second embodiment of the present invention is described here. The steps are substantially the same as those of the first embodiment, such as providing a wafer 110, providing a metal plate 120, and partially etching the metal plate 120. The upper layer 121, a process of combining the wafer Π0 to the upper layer 121 of the metal plate 120, and providing a bottom pad 130. After the wafer 110 is bonded to the upper layer 121 of the metal plate 120 and a bottom pad 130 is provided, that is, before the lower layer 122 of the metal plate 120 is etched and removed, a plurality of anti-corrosion spots 14 are coated on the metal plate.丨 2〇 The lower layer 122 is formed at the second end 125 corresponding to the upper layer 121, and is preferably formed by electroplating a low temperature eutectic alloy such as a nickel layer or a nickel-containing alloy [Ni / Pd / Au]. In the combined structure shown in FIG. 4a, in the last step of removing the lower layer 122 of the metal plate 120, it is to remove the lower layer 122 of the metal plate 120 by an etching method because the lower layer 122 is at the second end point 125 corresponding to the upper layer 121. The plating has a plurality of anti-corrosion spots, so that the lower layer

Page 11 V. Description of the invention (8) The corrosion prevention point of 1 2 2 1 4 0 will not be eroded ', so the chip size package structure shown in Figure 4b is obtained, in which the thickness of the second end point 125 [the upper layer 121 plus The lower layer 122] is larger than the thickness of the first terminal 124 [only the upper layer 121], so that the second terminal 125 protrudes beyond the bottom pad 130. Therefore, the second terminal 125 can be directly bonded to the circuit board with the chip size packaging structure. Of course, the above-mentioned step of coating a plurality of anti-corrosion spots 140 on a part of the lower layer 122 of the metal plate 120 or the step of plating a low-temperature eutectic alloy is not necessarily in the manufacturing steps of the present invention, and a metal plate may also be provided. In the step of 120, a plurality of anti-corrosion points [plating layers] have been formed on a part of the lower layer 122 of the metal plate 120, wherein the anti-corrosion points 140 in the lower layer 122 correspond to the second end points 125 in the upper layer 123, and Simplify manufacturing processes and increase manufacturing efficiency. In addition, the manufacturing method of the wafer size package of the present invention is not limited to the known wafer 110 near the periphery of the wafer 110 '. In the third and fourth embodiments of the present invention, it is revealed that the wafer 2 is of another type of pad distribution. Manufacturing method of wafer size package of i 〇. In the third specific embodiment of the present invention, the steps of the manufacturing method are the same as those of the first specific embodiment and another wafer is processed. The steps are as follows: Provide a wafer 210 (as shown in FIG. 5). The welding pad 211 of the wafer 210 is located on a middle line close to the front surface of the wafer 210; a metal plate 220 (as shown in FIG. 6) is provided; the upper layer 221 of the metal plate 22 is partially etched, except that a plurality of redistributions are formed In addition to the conductive line 223, a surrounding ring 227 is formed near the placement area 226 to restrict the bottom pad 230. The conductive line 22 3 runs from the first end point 224 to the second end point 25.

/ 157662 V. Description of the invention (9) Extends from the inside to the outside; Combines the wafer 2 10 to the placement area 226 of the upper layer 221 of the metal plate 2 2 0; Provides a bottom pad 230 on the upper layer of the wafer 210 and the metal plate 220 Between 221 [as shown in FIG. 7a]; and removing the lower layer 222 of the metal plate 220 by grinding or engraving [as shown in FIG. 7b]. In addition, in the fourth embodiment of the present invention, the steps of the manufacturing method are the same as those of the second embodiment and the wafer 2 1 0 is processed, that is, the lower layer 2 2 2 of the metal plate 2 2 0 is removed by etching. Previously, a plurality of anti-corrosion spots 240 were coated on the lower layer 222 of the metal plate 220 at the second end point 225 corresponding to the upper layer 221, such as a low temperature common electrodeposited nickel layer or a nickel-containing alloy [Ni / pd / Au :). The metal layer [eutectic meta 丨] is dissolved to form a combined structure as shown in FIG. 8a. Finally, the thickness of the gold chip size packaging structure 224 is removed by a shift etching method. Therefore, it should be understood that it is not clear. In order to limit the scope of the patent, the spirit of the present invention is protected. In the step of the protective layer of the invention, the layer 2 2 2 is based on the layer 2 22 below the plate 220 to obtain the crystal as shown in the figure. Wherein, the thickness of the second terminal 225 is larger than that of the first terminal, so that the second terminal 225 protrudes beyond the bottom pad 230, and is connected to the circuit board with the chip size packaging structure. The foregoing preferred embodiment is an example of the present invention. The invention is as follows: (1) The scope of protection of the invention shall be subject to the attached application. 'Any person skilled in the art will make any changes or modifications within the scope of: Belong to

Page 13 4 57 Brief description of the drawings [Illustration of the drawings] Figure 1: Top view of the wafer with solder pads located on the four sides of the front of the wafer; Figure 2: Partial etching of a metal plate according to the manufacturing method of the present invention to form at least one Top view corresponding to the redistribution circuit of the wafer of FIG. 1; FIG. 3a: a schematic cross-sectional view of the metal plate partially etched in FIG. 2 along line 3-3 according to the first embodiment of the present invention; Figure 3b: A schematic cross-sectional view of removing the lower layer of the metal plate from the combined structure of Figure 3a according to the first embodiment of the present invention; Figure 4a 圊: combining the wafer of Figure 1 to the second according to the second embodiment of the present invention Figure 4 is a schematic cross-sectional view of a partially etched metal plate along a line 3-3 after being partially plated; Figure 4b: a schematic cross-sectional view of the lower layer of the metal plate with the structural portion of Figure 4a removed according to a second embodiment of the invention; Figure 5: Top view of a wafer with solder pads located at a midline portion on the front of the wafer; Figure 6: Top view of a redistribution circuit corresponding to the wafer of Figure 5 formed by partially etching a metal plate according to the manufacturing method of the present invention Figure 7a: A schematic cross-sectional view taken along line 7-7 of a partially etched metal plate of Figure 5 combined with the wafer of Figure 5 according to the third embodiment of the present invention; Figure 7b: according to the third embodiment of the present invention The embodiment is a schematic sectional view of removing the lower layer of the metal plate by combining the structure of FIG. 7a; FIG. 8a: According to the fourth embodiment of the present invention, the wafer of FIG. 5 is combined with the partially etched metal plate of FIG. 6 and partially plated Trailing 7-7

Page 14 is a schematic illustration of a schematic diagram; and FIG. 8b 圊: a schematic cross-sectional view of the lower layer of the metal plate in accordance with the fourth embodiment of the present invention by combining the structure of FIG. 8a. [Illustration of figure number] 110 wafer 111 pad 112 bump 120 metal plate [lead frame] 121 upper layer 122 lower layer 123 conductive line [leading finger] 124 first terminal 125 second terminal 126 placement area 130 bottom pad [sealing compound ] 140 Anti-corrosion point 210 Wafer 211 Solder pad 212 Free block 220 Metal plate [lead frame] 221 Upper layer 222 Lower layer 223 Conductive circuit [Finger] 224 First end point 225 Second end point 226 Placement area 227 Surrounding part 230 Under pad [ Sealing gel] 240 Anti-corrosion point

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Claims (1)

6. Scope of Patent Application [Scope of Patent Application] 1. A method for manufacturing a chip-size package, the steps of which include at least: providing at least one wafer, wherein each wafer has a plurality of bonding pads; providing a metal plate, wherein the metal plate It is divided into an upper layer and a lower layer, and at least one placement area corresponding to the wafer is formed on the surface of the upper layer of the metal plate; the upper layer of the metal plate is partially etched to form a plurality of redistributed conductive circuits, and the plurality of conductive circuits Is carried by the lower layer of the metal plate and includes connected first and second endpoints, wherein the first endpoint corresponds to the pad of the wafer, and the second endpoint is dispersed in the placement area; Combine the above-mentioned wafer on the upper layer of the metal plate, and electrically connect the pads of the wafer and the first end of the conductive circuit; seal the front side of the wafer and the surface of the upper layer of the metal plate; and remove the metal plate Lower level. 2. The manufacturing method of the chip size package according to item 1 of the scope of the patent application, wherein in the above removing step, the lower layer of the metal plate is removed by grinding. 3. The manufacturing method of the chip size package according to item 1 of the scope of the patent application, wherein in the above removing step, the lower layer of the metal plate is removed by etching. 4. The method for manufacturing a chip size package according to item 3 of the scope of the patent application, further comprising the steps of: before etching and removing the lower layer of the metal plate, coating a plurality of anti-corrosion spots on the lower layer of the metal plate, wherein the The anti-corrosion point corresponds to the second endpoint of the upper conductive line. 457662 6. Scope of patent application 5. The manufacturing method of wafer size sealing according to item 4 of the scope of patent application, in which the anti-money point coating method is a key lock or alloy recording. 3. The manufacturing method of the chip size package according to item 1 of the patent application scope, wherein in the dream step of providing a metal plate, a plurality of anti-corrosion points are formed on the lower surface of the metal plate, and the anti-corrosion points correspond to At the second end of the upper conductive line. 7 'The manufacturing method of the chip-size package according to item 6 of the patent application', wherein the anti-corrosion point is nickel or a nickel alloy. 8. The method for manufacturing a chip-size package according to item 1 of the scope of the patent application, wherein bumps are formed on the plurality of bonding pads of the at least-wafer to electrically connect the conductive lines of the metal plate with a flip-chip type. First endpoint. 9 According to the manufacturing method of the chip size package described in item 8 of the scope of patent application, wherein in the sealing step, it is formed with a bottom pad between the front surface of a wafer and the surface of the upper layer of the metal plate. The combining step and the sealing step are performed simultaneously. 〃 10. The manufacturing method of the chip size package according to item 1 of the scope of the patent application, wherein in the step of partially etching the upper layer of the metal plate, the upper layer of the metal plate is etched to form a surround close to the placement area. Seal with glue. 11. A chip-size package structure, which mainly comprises: at least one chip having a plurality of pads on its bottom surface and bumps formed on the re-soldering pad; a plurality of redistributed conductive lines, and the plurality of conductive lines Formed by a metal plate and each having a first terminal and a second terminal connected by Sb 457662 6. Patent application scope ^-a pad in which the first terminal is bonded to the at least one wafer by the bump, and The two endpoints are scattered on the bottom surface of the corresponding wafer; and a yoke body is located between the bottom surface of the wafer and a plurality of mine guides. The structure of Dianchen Road, thickness 1 2. According to the chip size seal described in item 11 of the scope of the patent application, the second endpoint of the conductive circuit has a greater degree than the first endpoint 0 1 3. According to the patent application The wafer size package structure described in the range item π, wherein the pads of the wafer are close to the periphery of the bottom surface of the wafer. 14. The chip size package structure according to item 11 of the scope of the patent application, wherein the pad of the wafer is close to a middle portion of the bottom surface of the wafer. 15. A method for manufacturing a semiconductor package structure, the steps of which include at least: 3 & for at least one wafer 'each of which has a plurality of pads on the front surface; part of the surname is engraved with a layer above the lead frame to form a plurality of fingers, and the plurality of fingers are carried by the lower layer of the lead frame and The first end and the second end are connected, wherein the first end is vertically and vertically corresponding to the pads of the wafer, and the plurality of second ends are distributed uniformly and mutually with each other, which is used as the above-mentioned wafer redistribution. An external electrical connection point; the above chip is bonded to the upper layer of the lead frame in a flip-chip type, and the pads of the chip are electrically connected to the first ^ »1» end of the lead frame, Providing a base pad between the chip and the upper layer of the lead frame; and ά 89122018 The " guide ^ under the wire rack said correction bow I mean. 16. The manufacturing method according to the scope of the patent application, wherein the lead frame is underneath. ^ 7. Manufacturing method according to the scope of the patent application 'Before the other steps, the multiple anti-points are covered corresponding to the upper reference index 18. The manufacturing method is based on the scope of the patent application, where the surface shape of the lower layer of some lead frames should be The reference layer of the upper layer, the removal step of item 15 is as follows: the money is at the second end. The semiconductor package described in item 15 is a step of etching a layer above a lead frame to form a plurality of anti-corrosion spots, and the second terminal is protected. The bottom pad is a semiconductor package step for fixing the lead frame, and the lower layer of the lead frame is removed by etching the semiconductor package. The structure is manufactured by removing the lower layer of the structure and preventing the corrosion. In the structural steps, this point is considered