TW533518B - Substrate for carrying chip and semiconductor package having the same - Google Patents

Substrate for carrying chip and semiconductor package having the same Download PDF

Info

Publication number
TW533518B
TW533518B TW091110599A TW91110599A TW533518B TW 533518 B TW533518 B TW 533518B TW 091110599 A TW091110599 A TW 091110599A TW 91110599 A TW91110599 A TW 91110599A TW 533518 B TW533518 B TW 533518B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
metal layer
patent application
core layer
Prior art date
Application number
TW091110599A
Other languages
Chinese (zh)
Inventor
Wen-Da Tsai
Jiun-Ren Huang
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW091110599A priority Critical patent/TW533518B/en
Application granted granted Critical
Publication of TW533518B publication Critical patent/TW533518B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A substrate for carrying a chip is provided, which includes a core layer defined with a chip attach area on which at least one metallic layer is formed. The metallic layer is of a central portion, a peripheral portion surrounding the central portion and formed with a plurality of vias, and a plurality of bridging portions for interconnecting the central portion and the peripheral portion. A solder mask layer is applied over the metallic layer, which leaves the chip attach area of the core layer uncovered by the metallic layer to be exposed to the solder mask layer. A plurality of openings are formed in the solder mask layer so as to expose the metallic layer connecting the openings. By exposing the chip attach area of the core layer uncovered by the metallic layer to the solder mask layer, the adhesive applied to the chip attach area for adhering a chip to the substrate can be in direct contact with the core layer. It thus enhances the reliability and quality of packages thus obtained.

Description

533518 五、發明說明(1) [發明領域] 本發明係有關一種基板,尤指一種適用於半導體封裝 件且作為晶片承載件之基板,以及使用該基板之半導體封 裝件。 [背景技術說明] 習知球柵陣列式(Bal 1 Grid Array,BGA)半導體封裝 件用之基板,係於基板之晶片接置區(chip Attach Area) 上形成一金屬層(通常為銅層),並敷設一拒銲劑(s〇lder Mask)層至該基板上,該拒銲劑層開設有多數開孔,以使 該金屬層之預定部位得藉該開孔而外露出拒銲劑層。而 後,塗覆一膠黏劑(Adhesive)於晶片接置區之拒銲劑層及 外露之金屬層上,俾將一晶片藉膠黏劑而黏接於基板上。 然而’此種設計具有諸多缺點,首先,上述金屬層係完整 覆蓋住晶片接置區,使敷設至晶片接置區之拒銲劑層僅得 附著於該金屬層上;由於拒銲劑對金屬之附著性不佳,故 易發生脫層(Del ami nation)等問題。再者,塗覆於晶片接 置區之膠黏劑僅與拒銲劑層及金屬層接觸,由於膠黏劑對 金屬之附者性不佳’故易於膠黏劑與金屬層間發生脫層, 進而蔓延至膠黏劑與拒銲劑層間亦產生脫層,造成晶片與 基板之黏接嚴重受損。 有鑑於此,美國專利案第5,703,402、 5,216,478及5, 409, 863號遂發展出另一種BGA半導體封裝件用之基板1, 如第4A及4B圖所示’其特徵在於該基板1之晶片接置區1〇 以輻射狀(Sun Ray)方式形成一金屬層1 !,以使部份之晶533518 V. Description of the invention (1) [Field of the invention] The present invention relates to a substrate, particularly a substrate suitable for a semiconductor package and used as a wafer carrier, and a semiconductor package using the substrate. [Background Description] A conventional substrate for a Ball Grid Array (BGA) semiconductor package is a metal layer (usually a copper layer) formed on a chip attach area of the substrate, and A solder mask layer is laid on the substrate, and the solder mask layer is provided with a plurality of openings, so that a predetermined portion of the metal layer can expose the solder mask layer by the openings. Then, an adhesive (Adhesive) is applied on the solder resist layer and the exposed metal layer of the wafer receiving area, and a wafer is adhered to the substrate by the adhesive. However, this design has many disadvantages. First, the above metal layer completely covers the wafer interface area, so that the solder resist layer applied to the wafer interface area can only be attached to the metal layer; due to the adhesion of the solder resist to the metal Poor sex, so prone to problems such as delamination (Del ami nation). In addition, the adhesive applied to the wafer receiving area is only in contact with the solder resist layer and the metal layer. Due to the poor adhesion of the adhesive to the metal, it is easy to delaminate between the adhesive and the metal layer, and further Delamination spreading between the adhesive and the solder resist layer also caused serious damage to the adhesion between the chip and the substrate. In view of this, U.S. Patent Nos. 5,703,402, 5,216,478 and 5,409,863 developed another substrate 1 for BGA semiconductor packages, as shown in Figures 4A and 4B. 'Characterized by the wafer connection of the substrate 1 The placement region 10 forms a metal layer 1 in a Sun Ray manner so that part of the crystal

16603.ptd 第6頁 53351816603.ptd Page 6 533518

片接置區10未以該金屬層11所覆蓋(即晶片接置區1〇之區 域R)。敷設一拒銲劑層12於該基板1上,該拒銲劑層12並 開設有多數開孔120以使預定部位11〇之金屬層丨丨外露出該 拒銲劑層1 2 ;該金屬層丨1之外露部位i丨〇係作為散执墊 (Thermal Pad),以令後續承載於晶片接置區1〇上^晶片 (未圖示)得藉該散熱墊而散逸熱量至外界。此種輻射狀之 金屬層11,使拒銲劑層1 2得直接附著於晶片接置區丨〇上未 以金屬層1 1所覆盍之區域R,俾增進拒婷劑層1 2斑基板1之 結合力’以改善附著性不佳造成之脫層等問題。 然而,如第4C圖所示,使用上述基板i進行黏晶作 業’將一膠黏劑1 3塗覆至晶片接置區1 〇上以供黏接晶片^ 4 時,該膠黏劑1 3僅附著於拒銲劑層丨2及金屬層n,仍無法 解決膠黏劑與基板間結合力不足、易產生脫層等缺點;同 時,附著性不佳之膠黏劑亦容易導致膠黏劑分布不均,而 造成溢膠於晶片接置區外' 於晶片角落形成氣洞(v〇 i d)等 問題,於後續高溫製程中,氣洞存在極易弓丨發之氣爆 (Popcorn)現象,嚴重損害製成品之品質及良率。再者, 金屬層11之外露部位(散熱墊)11〇之設置數量不足,無法 有效率地使晶片14運作產生之熱量散逸至外界,如此可能 因過熱而影響製成品之信賴性。 因此,如何發展出一種基板,得有效增進膠黏劑與基 板間結合力’並改善晶片之散熱效率,實為必要探討之課 題。 [發明概述]The wafer-receiving region 10 is not covered by the metal layer 11 (that is, the region R of the wafer-receiving region 10). A solder resist layer 12 is laid on the substrate 1, and the solder resist layer 12 is provided with a plurality of openings 120 so that the metal layer at a predetermined portion 110 is exposed to the solder resist layer 12; the metal layer 1 The exposed part i 丨 〇 is used as a thermal pad, so that subsequent wafers (not shown) carried on the wafer receiving area 10 can use the heat dissipation pad to dissipate heat to the outside. Such a radial metal layer 11 enables the solder resist layer 12 to be directly attached to the wafer receiving area. The area R that is not covered with the metal layer 1 1 enhances the tinting resist layer 1 2 and the spotted substrate 1 Binding force 'to improve delamination caused by poor adhesion. However, as shown in FIG. 4C, the above-mentioned substrate i is used for the die-bonding operation. When an adhesive 13 is applied to the wafer receiving area 10 for bonding the wafer ^ 4, the adhesive 1 3 Adhering only to the solder resist layer 2 and the metal layer n cannot solve the shortcomings such as insufficient bonding force between the adhesive and the substrate, and easy to cause delamination; meanwhile, the adhesive with poor adhesion also easily leads to the uneven distribution of the adhesive This can cause problems such as overflowing glue outside the wafer receiving area, and forming voids at the corners of the wafer. In subsequent high-temperature processes, there is a popcorn phenomenon that can easily occur. Damage the quality and yield of finished products. In addition, the number of exposed portions (heat-dissipating pads) 11 of the metal layer 11 is insufficient to efficiently dissipate heat generated from the operation of the chip 14 to the outside, which may affect the reliability of the finished product due to overheating. Therefore, how to develop a substrate that can effectively improve the bonding force between the adhesive and the substrate 'and improve the heat dissipation efficiency of the chip is a subject that must be discussed. [Invention Overview]

16603.ptd 第7頁 53351816603.ptd Page 7 533518

本發明之一目 及使用該基板之半 敷設至基板之芯層 間之結合力,並控 保製成品之品質及 的在於提供一種作為 導體封裝件,使黏晶 (Core Layer)上,以 制膠黏劑溢膠、分布 信賴性。 曰曰曰片承載件之基板· 用之膠黏劑得直接 增進膠黏劑與基板 不均等狀況,俾確 供^^種作发θ T為曰日片承載件之基 件’設置盤β夕 直數1多之散熱墊 運作產生之為3 ^ 王之熱I,俾改善 本發明之另一目的在於提 板及使用該基板之半導體封裝 (Thermal Pad)以有效散逸晶片 整體封裝結構之散熱效率。 為達成上揭及其他目的’本發明揭露一種 載件之基板及使用該基板之半導體封袭件。該Α板$包 括:一芯層,於其至少一表面上界定有至少::二片接=區 (Chip Attach Area),·至少一金屬層,形成於該芯層之晶 片接置區上,該金屬層具有一中心部、一圍繞該中心部之 周邊部、及多數連接該中心部與周邊部之連接部,其中, 該周邊部開設有多數貫穿該金屬層之槽孔,以使該槽孔内 之區域之芯層外露出該金屬層;以及一拒銲劑(Solder Mask)層,敷設至該金屬層上,以使該晶片接置區上未以 該金屬層所覆蓋之區域之芯層(即相鄰連接部間之區域之 芯層以及外露於該金屬層槽孔内之芯層)外露出該拒銲劑 層,其中,該拒銲劑層於對應至該金屬層之中心部及連接 部之預定部位上開設有多數貫穿該拒銲劑層之開孔’藉之 以令該預定部位之中心部及連接部之金屬層外露出該拒銲 劑層並作為散熱墊,以令接置於該晶片接置區上之晶片得One aspect of the present invention and the use of the bonding force between the semi-layout of the substrate and the core layer of the substrate, and controlling the quality of the finished product, is to provide a conductor package, which can be used on the core layer to make adhesive. Agent overflow, distribution reliability. The substrate of the wafer carrier · The adhesive used can directly improve the unevenness of the adhesive and the substrate, and it is sure to provide ^^ for making hair θ T is the base member of the wafer carrier 'set plate β evening Counting more than one thermal pad operation results in 3 ^ King of Heat I. Another improvement of the present invention is to lift the board and use the substrate's semiconductor package (Thermal Pad) to effectively dissipate the heat dissipation efficiency of the overall package structure of the chip. . In order to achieve the above disclosure and other purposes, the present invention discloses a substrate of a carrier and a semiconductor package using the substrate. The A plate includes: a core layer, at least one surface of which is defined with at least: two chip attachment areas (Chip Attach Area), at least one metal layer formed on the wafer interface area of the core layer, The metal layer has a central portion, a peripheral portion surrounding the central portion, and a plurality of connecting portions connecting the central portion and the peripheral portion, wherein the peripheral portion is provided with a plurality of slot holes penetrating the metal layer to make the slot The metal layer is exposed from the core layer in the area inside the hole; and a Solder Mask layer is laid on the metal layer so that the core layer in the area where the wafer is not covered by the metal layer (That is, the core layer in the area between adjacent connection portions and the core layer exposed in the slot of the metal layer) the solder resist layer is exposed, wherein the solder resist layer corresponds to the center portion and the connection portion corresponding to the metal layer The predetermined portion is provided with a plurality of openings penetrating through the solder resist layer, so that the metal layer of the center portion and the connection portion of the predetermined portion is exposed to the solder resist layer and serves as a heat dissipation pad, so as to be placed on the wafer. Wafers on the contact area

16603,ptd 第8頁 533518 五、發明說明(4) 藉該散熱墊而散逸熱量至外界。 使用上述基板之半導體封裝件結構,係將膠黏劑(如 銀膠’ Silver Paste)敷設至晶片接置區上之拒銲劑層、 外露出該拒銲劑層之芯層及外露出該拒銲劑層之金屬層· 然後,藉該膠黏劑而將一晶片黏接於該基板之晶片接置區 上’再進行銲線(Wire Bonding)、模壓(Molding)、植球°° (Implantation)等製程而完成本發明之半導體封裝件。 由於膠黏劑與樹脂材質之芯層間之黏結性優於膠黏劑 與拒銲劑間之黏結性,因此,大幅減少晶片接置區上以担 銲劑層覆蓋之面積,而使部份芯層(如相鄰連接部間之區 域之芯層等)外露以與膠黏劑直接黏接,得有效增進該膠 黏劑與基板間之結合力,俾摒除習知技術上因膠黏劑與担 銲劑之黏結性不佳而可能導致脫層等之缺點。同時,金屬 層之周邊部開設有多數槽孔,並使該槽孔内之區域之芯層 亦外露出拒銲劑層而得與膠黏劑直接黏結,除進一步增加 膠黏劑與基板結合力之功效外,復可有效控制膠黏劑之溢 膠狀況,俾使膠黏劑不致溢膠至晶片接置區外而產生不當 之溢膠、爬膠等問題’以確保黏晶作業之品質。因此,大 幅增加膠黏劑與芯層直接接觸之面積,得改善習知膠黏劑 分布不均、於晶片角落形成氣洞(Vo i d)等問題,避免氣洞 引起之氣爆(Popcorn)現象,俾確保基板、晶片之結構完 整性以及製成品之良率。 再者,相較於習知基板僅於金屬層之中心部上形成數 量少之散熱墊,本發明之金屬層則同時於中心部及連接部16603, ptd page 8 533518 V. Description of the invention (4) Dissipate heat to the outside world through the heat sink. The semiconductor package structure using the above substrate is an adhesive (such as silver paste) is applied to a solder resist layer on a wafer receiving area, a core layer exposing the solder resist layer, and the solder resist layer is exposed. Metal layer · Then, by using the adhesive, a wafer is adhered to the wafer receiving area of the substrate, and then processes such as wire bonding, molding, and implantation are performed. The semiconductor package of the present invention is completed. Because the adhesion between the adhesive and the core layer of the resin material is better than the adhesion between the adhesive and the solder resist, the area covered by the solder layer on the wafer contact area is greatly reduced, and part of the core layer ( (Such as the core layer in the area between adjacent connection parts) is exposed to directly adhere to the adhesive, which can effectively improve the bonding force between the adhesive and the substrate, and eliminate conventional adhesives and soldering fluxes. It has poor adhesion and may cause defects such as delamination. At the same time, the periphery of the metal layer is provided with a large number of slots, and the core layer in the area of the slot is also exposed with a solder resist layer to directly bond with the adhesive, in addition to further increasing the bonding force between the adhesive and the substrate In addition to its effectiveness, the compound can effectively control the overflow of the adhesive, so that the adhesive does not overflow outside the wafer receiving area and cause problems such as improper overflow and creeping, to ensure the quality of the sticking operation. Therefore, the direct contact area between the adhesive and the core layer is greatly increased, and the problems such as uneven distribution of the adhesive and the formation of air holes (Vo id) in the corners of the wafer can be improved to avoid popcorn caused by air holes. To ensure the structural integrity of the substrate and wafer and the yield of the finished product. In addition, compared with the conventional substrate in which only a small number of heat dissipation pads are formed on the center portion of the metal layer, the metal layer of the present invention is provided on the center portion and the connection portion at the same time.

ϋΙΙΗΙ 16603.ptd 第9頁 533518 五、發明說明(5) 上佈設散熱墊,且大幅增加散熱墊之設置數目,故得有效 改善散熱功效,使晶片運作產生之熱量有效率地散逸至外 界,而不致因過熱而影響製成品之信賴性。 [發明之詳細說明] 以下即配合所附之第1至3圖詳細説明本發明所揭露之 基板以及使用該基板之半導體封裝件,惟該等各圖俱為簡 化之圖示’僅以示意方式顯示與本發明有關之結構單元, 且此些結構單元並非以實際數量或尺寸比例繪製,實際之 基板與半導體封裝件之結構佈局應更加複雜。 第1、2 A及2 B圖係分別顯示本發明之基板2之上視圖及 剖視圖。 如圖所示,該基板2係包括:一怒層(C 〇 r e Layer) 20 ;至少一金屬層21,形成於該芯層20之晶片接置 區(Chip Attach Area)202上;以及一拒銲材質層22,敷 設至該金屬層2 0,而令晶片(未圖示)得於後續製程中承載 至該晶片接置區2 0 2上。 首先’製備'層20’該芯層20係以琢氧樹脂(E p 〇 X y Resin)、聚亞醯胺(p〇ly imide)樹脂、βΤ樹脂或FR4樹脂等 習用製造基板之樹脂材料製成,故於此不復詳述芯層之製 法。該芯層20具有一上表面200及一相對之下表面201 ;該 上表面200界定有至少一晶片接置區202,該晶片接置區 202係供後續黏晶之用;該晶片接置區2〇2並開設有多數貫 穿芯層2 0之貫孔(V i a ) 2 0 3,該貫孔2 0 3係後續作為散熱貫、 孔(Thermal Vi a)(容後詳述)。 ”、、ϋΙΙΗΙ 16603.ptd Page 9 533518 V. Description of the invention (5) The heat dissipation pads are arranged and the number of heat dissipation pads is greatly increased, so the heat dissipation efficiency can be effectively improved, and the heat generated by the chip operation can be efficiently dissipated to the outside world, Do not affect the reliability of the finished product due to overheating. [Detailed description of the invention] The following is a detailed description of the substrate disclosed by the present invention and the semiconductor package using the same in conjunction with the attached drawings 1 to 3, but these drawings are simplified diagrams. The structural units related to the present invention are shown, and these structural units are not drawn according to the actual number or size ratio, and the actual structural layout of the substrate and the semiconductor package should be more complicated. Figures 1, 2 A and 2 B are respectively a top view and a cross-sectional view of the substrate 2 of the present invention. As shown in the figure, the substrate 2 includes: a Co layer 20; at least one metal layer 21 formed on a chip attach area 202 of the core layer 20; and a resist layer The solder material layer 22 is laid on the metal layer 20 so that a wafer (not shown) can be carried on the wafer receiving area 202 in a subsequent process. First, the "layer 20" is prepared. The core layer 20 is made of a resin material for conventional substrates, such as an oxygen resin (Ep 0x y Resin), a polyimide resin, a βT resin, or a FR4 resin. Therefore, the manufacturing method of the core layer will not be described in detail here. The core layer 20 has an upper surface 200 and a relatively lower surface 201; the upper surface 200 defines at least one wafer receiving area 202, which is used for subsequent die bonding; the wafer receiving area A plurality of via holes (Via) 203 which penetrate through the core layer 20 are provided in the 002, and the via holes 203 are used as thermal vias (Thermal Vias) (described later in detail). ",,

16603.ptd 第10頁 533518 五、發明說明(6) 然後,於該芯層20之上、下表面2 0 0、201上形成預定 電路佈局如導電跡線(Conductive Trace,未圖示)等, 其中,該芯層20之晶片接置區202上佈置有一金屬層(如銅 ^等)21,且該貫孔内壁上鍍有導熱性金屬(如銅等), 以使熱能或熱量得自該金屬層2 1經由貫孔2 0 3而傳導至佈 役於該芯層20下表面201上之散熱墊(Thermal Pad)204。 該導電跡線、金屬層21及散熱墊204之製法,係將壓合至 該芯層20上、下表面200、201上之銅箔(未圖示),施以習 知曝光(Exposing)、顯影(Developing)、蝕刻(Etching) 等作業而使其圖案化(Patterning),以形成預定之電路佈 局;此製法係屬習知,故於此不予贅述。 該怒層20晶片接置區202上之金屬層21,具有一中心 部2 1 0、一圍繞該中心部2 1 0之周邊部2 1 1、及多數連接該 中心部210與周邊部211之連接部212;該金屬層21之作 用,在於與後續載接至晶片接置區2 0 2上之晶片(未圖示) 之電性及導熱性連通。 由於銅質金屬層2 1與芯層2 0之樹脂材質間之附著性不 佳,該金屬層21係採用輻射狀(Sun Ray)之設計,即該金 屬層2 1之連接部2 ;! 2係呈類似光芒狀方式排列,如第1圖所 不(連接部212之設置數目不限於圖示者)。如此,晶片接 ,區201上未以該金屬層21所覆蓋之區域之芯層,即相 邮連接部2 1 2間之區域R1之芯層2 0,得外露出該金屬層 同時’為取得附著力與導熱(或散熱)功效之平衡,該 金屬層21之尺寸需適中;若金屬層21過小,則會影響散熱16603.ptd Page 10 533518 V. Description of the invention (6) Then, a predetermined circuit layout such as a conductive trace (not shown) is formed on the core layer 20 and the lower surface 2 0, 201. A metal layer (such as copper, etc.) 21 is arranged on the wafer receiving area 202 of the core layer 20, and a thermally conductive metal (such as copper, etc.) is plated on the inner wall of the through hole, so that the thermal energy or heat is obtained from the The metal layer 21 is conducted to the thermal pad 204 disposed on the lower surface 201 of the core layer 20 through the through hole 203. The conductive trace, the metal layer 21 and the heat dissipation pad 204 are manufactured by laminating copper foils (not shown) on the upper and lower surfaces 200 and 201 of the core layer 20 with conventional exposure (Exposing), Development (Etching) and other operations to pattern it to form a predetermined circuit layout; this manufacturing method is known, so it will not be repeated here. The metal layer 21 on the wafer receiving area 202 of the angry layer 20 has a central portion 2 1 0, a peripheral portion 2 1 1 surrounding the central portion 2 1 0, and a plurality of connecting portions between the central portion 210 and the peripheral portion 211. The connection portion 212; the function of the metal layer 21 is to electrically and thermally communicate with a wafer (not shown) subsequently mounted on the wafer receiving area 202. Due to the poor adhesion between the copper metal layer 21 and the resin material of the core layer 20, the metal layer 21 adopts a Sun Ray design, that is, the connection portion 2 of the metal layer 21;! 2 They are arranged in a similar light-like manner, as shown in FIG. 1 (the number of the connecting portions 212 is not limited to those shown in the figure). In this way, the wafer is connected, and the core layer of the area 201 that is not covered by the metal layer 21, that is, the core layer 20 of the region R1 between the photo-connecting sections 2 12 is exposed, and the metal layer is exposed at the same time. The balance between adhesion and thermal conductivity (or heat dissipation) effect, the size of the metal layer 21 needs to be moderate; if the metal layer 21 is too small, it will affect heat dissipation

533518 五 發明說明(7) 功效;若金屬層21過大,則導致附著力差,而易造成金屬· 層21與芯層20間之脫層(Del ami nation)。由於該輻射狀或 光芒狀金屬層21之設計係屬習知,故於此不予贅述。 再者’該金屬層21之周邊部211開設有多數貫穿金屬 層2 1之槽孔2 1 3,以使該槽孔2 1 3内之區域R 2之芯層2 〇外露 出該金屬層21。 最後,敷設一拒銲材質層22如拒銲劑等(s〇lde:f Mask)至該芯層20之上、下表面2〇{)、2〇1上,以覆蓋該芯 層2 0上之電路佈局,俾形成一保護層而令導電跡線等與外 界氣密隔離,使其免於氧化或受外力、污染物 (Contaminant)侵害之虞。 選擇性(S e 1 e c t i v e )移除部份之拒銲材質層2 2,以使 該芯層20下表面201上之散熱墊2〇4外露出該拒銲材質層 22,並使敷β又至日曰片接置區202上之拒銲材質層22僅遮覆 住該金屬層20,而令該晶片接置區2〇2上未以該金屬層21 所覆蓋之區域之芯層2 0,即相鄰連接部2 1 2間之區域r丨之 芯層2 0以及外露於周邊部2 1 1槽孔2 1 3内之芯層2 fU F B R2),皆外露出該拒鋒材質層22。 曰2〇(£域 再者,該拒銲材質層2 2開設有多數貫穿拒銲材質層2 2 之開孔22 0,該開孔22 0係對應至該金屬層21之中心部2\〇 及連接部2 1 2上之預定部位,以令該預定部位之中心部2丄〇 及連接部2 1 2之金屬層2 1得藉該開孔220而外露出該拒鲜材 質層22。該中心部210及連接部212之外露之金屬層/部位係 作為散熱墊214’以令後續接置於該晶片接置區2Q2上之〶533518 V Description of the invention (7) Effect; if the metal layer 21 is too large, it will lead to poor adhesion, and it will easily cause delamination between the metal layer 21 and the core layer 20 (Del ami nation). Since the design of the radial or radiant metal layer 21 is conventional, it will not be repeated here. Furthermore, the peripheral portion 211 of the metal layer 21 is provided with a plurality of slot holes 2 1 3 penetrating through the metal layer 21 so that the core layer 2 of the region R 2 within the slot hole 2 1 3 exposes the metal layer 21. . Finally, a solder resist material layer 22, such as a solder resist (f mask), is laid on the core layer 20 above, the lower surface 20 {), and 201 to cover the core layer 20. The circuit layout prevents the conductive traces from being air-tightly isolated from the outside by forming a protective layer, which protects them from the risk of being oxidized or subject to external forces and contaminants. Selectively (S e 1 ective) remove a part of the solder resist material layer 22 so that the heat radiation pad 204 on the lower surface 201 of the core layer 20 exposes the solder resist material layer 22 and make the applied β To date, the solder-repellent material layer 22 on the wafer receiving area 202 only covers the metal layer 20, and the core layer 20 on the wafer receiving area 202 is not covered by the metal layer 21 That is, the core layer 20 in the area r 丨 between the adjacent connection portions 2 1 2 and the core layer 2 fU FB R2 exposed in the peripheral portion 2 1 1 slot 2 1 3), the anti-front material layer is exposed. twenty two. In addition, the solder resist material layer 22 is provided with a plurality of openings 22 0 penetrating through the solder resist material layer 2 2, and the opening holes 22 0 correspond to the central portion 2 of the metal layer 21. And a predetermined portion on the connection portion 2 1 2 so that the center portion 20 of the predetermined portion and the metal layer 21 of the connection portion 2 12 may expose the fresh-repellent material layer 22 through the opening 220. The The exposed metal layers / parts of the central portion 210 and the connecting portion 212 are used as heat dissipation pads 214 'to allow subsequent placement on the wafer receiving area 2Q2.

533518 五、發明說明(8) 片(未圖示)運作產生之熱量,得經由該散熱墊214、散熱 貫孔203及散熱墊204而散逸至外界。相較於習知基板僅於 金屬層之中心部上形成數量少之散熱墊,本發明之金屬層 2 1則同時於中心部2 1 0及連接部2 1 2上佈設散熱墊2 〇 4,且 大幅增加散熱墊2 0 4之設置數目,故得有效改善散熱功 效,使晶片運作產生之熱量有效率地散逸至外界,而不致 因過熱而影響製成品之信賴性。533518 V. Description of the invention (8) The heat generated by the operation of the tablet (not shown) can be dissipated to the outside through the heat dissipation pad 214, the heat dissipation through hole 203, and the heat dissipation pad 204. Compared with the conventional substrate, only a small number of heat radiation pads are formed on the center portion of the metal layer, the metal layer 21 of the present invention is provided with a heat radiation pad 2 on the center portion 2 10 and the connection portion 2 12 at the same time. And the number of heat sink pads 204 is greatly increased, so the heat dissipation effect can be effectively improved, and the heat generated by the chip operation can be efficiently dissipated to the outside without affecting the reliability of the finished product due to overheating.

第3A至3D圖係顯示使用上述基板2之半導體封裝件之 製程示意圖。下述僅以球栅陣列(Bali GHd Array,BGA) 封裝件為例說明,然本發明之範疇不以此為限。 首先,如第3A圖所示,製備一上述基板2,並於該基 板2之晶片接置區202上敷設一膠黏劑23如銀膠(Silver Paste)等,使該膠黏劑23塗覆於該晶片接置區2〇2上之拒 焊材質層22、外露出該拒銲材質層22之芯層2〇及外露出該 拒銲材質層22之金屬層21。3A to 3D are schematic diagrams showing a manufacturing process of a semiconductor package using the above-mentioned substrate 2. The following description only uses a ball grid array (Bali GHd Array, BGA) package as an example, but the scope of the present invention is not limited thereto. First, as shown in FIG. 3A, a substrate 2 is prepared, and an adhesive 23 such as Silver Paste is applied on the wafer receiving area 202 of the substrate 2 to coat the adhesive 23. A solder resist material layer 22 on the wafer receiving area 202, a core layer 20 on which the solder resist material layer 22 is exposed, and a metal layer 21 on which the solder resist material layer 22 is exposed.

由於該膠黏劑23與芯層20(樹脂材質)間之黏結性優} 膠黏劑23與拒銲材質層(拒銲劑)22間之黏結性,因此,; 幅減少該晶片接置區2 0 2上以拒銲材質層22覆蓋之面積, =使部=芯層20(例如相鄰連接部212間之區域以之芯層$ 進兮t溆不)外露以與膠黏劑23直接黏接,得有效J m ^ m . 與基板2間之結合力,俾摒除習知技術上因 之黏結性不佳而可能導致脫層等之缺點 槽孔2 1 3内之曰F \之周邊部2 11開設有多數槽孔2 1 3,並使1 曰 品域R2之芯層20亦外露出拒銲材質層22而得Because the adhesiveness between the adhesive 23 and the core layer 20 (resin material) is excellent} The adhesiveness between the adhesive 23 and the solder resist material layer (solder resist) 22, therefore, the width of the wafer receiving area is reduced 2 The area covered by the solder-resistant material layer 22 on 02, = make part = core layer 20 (for example, the core layer $ in the area between adjacent connection parts 212 is not exposed) is exposed to directly adhere to the adhesive 23 The effective joint force between J m ^ m and the substrate 2 is to eliminate the shortcomings of the conventional technology, such as poor adhesion, which may cause delamination, etc., and the peripheral part of the slot 2 1 3 2 11 is provided with a plurality of slot holes 2 1 3, and the core layer 20 of the product domain R2 is also exposed to the solder resist material layer 22

16603.ptd 第13頁 533518 五、發明說明(9) 與膠黏劑2 3直接黏結,除進一步增加膠黏劑2 3與基板2結 · 合力之功效外,復可有效控制膠黏劑2 3之溢膠狀況,俾使 膠黏劑2 3不致溢膠至晶片接置區2 0 2外而產生不當之溢 膠、爬膠等問題,以確保黏晶作業之品質。因此,大幅增 加膠黏劑2 3與芯層2 0直接接觸之面積,得改善習知膠黏劑 分布不均、於晶片角落形成氣洞(V 〇 i d )等問題,避免氣洞 引起之氣爆(Popcorn)現象,俾確保製成品之結構完整性 及良率。 然後,如第3B圖所示,進行一黏晶作業,將一晶片24 藉該膠黏劑2 3而黏接於該基板2之晶片接置區2 0 2上; 接著,如第3C圖所示,進行一銲線(Wire Bonding)作 業,將多數銲線2 5銲接至該晶片2 4與基板2上,藉之以使 該晶片24電性連接至該基板2。 最後,如第3D圖所示,進行一模壓(Molding)作業以 樹脂化合物(如環氧樹脂)形成一封裝膠體 (Encapsulant)26,該封裝膠體26與基板2結合用以包覆承 載於基板2上之晶片2 4及銲線2 5,俾令該晶片2 4及銲線2 5 與外界氣费隔離’而不致受外界衝擊(Ifflpact)或污染物侵 害。而後’進行一植球(Implantation)作業,以植設多數 銲球27於該基板2上,該銲球27外露出該封裝膠體26,並 作為半導體封裝結構之輸入/輸出端(InpUt/Qu^put Connection),以使晶片24得藉銲球27而與外界裝置(未圖 示)電性連接。16603.ptd Page 13 533518 V. Description of the invention (9) Adhesion directly to the adhesive 2 3, in addition to further increasing the effect of the adhesion and synergy between the adhesive 2 3 and the substrate 2, the compound can effectively control the adhesive 2 3 The overflowing glue condition prevents the adhesive 23 from overflowing outside the wafer receiving area 2 02 and causing problems such as improper overflowing and creeping, to ensure the quality of the sticking operation. Therefore, the area of direct contact between the adhesive 23 and the core layer 20 is greatly increased, and the problems of uneven distribution of the adhesive and the formation of air holes (V oid) in the corners of the wafer can be improved to avoid the gas caused by the air holes. Popcorn phenomenon, to ensure the structural integrity and yield of finished products. Then, as shown in FIG. 3B, a die bonding operation is performed, and a wafer 24 is bonded to the wafer receiving area 202 of the substrate 2 by the adhesive 23, and then, as shown in FIG. 3C As shown, a wire bonding operation is performed, and a plurality of bonding wires 25 are soldered to the wafer 24 and the substrate 2, so that the wafer 24 is electrically connected to the substrate 2. Finally, as shown in FIG. 3D, a molding operation is performed to form an encapsulant 26 from a resin compound (such as epoxy resin). The encapsulant 26 is combined with the substrate 2 to cover and carry the substrate 2. The wafer 24 and the bonding wire 25 on the wafer 24 and the bonding wire 25 are separated from the outside air, so as not to be affected by external impact (Ifflpact) or pollutants. Then, an “implantation” operation is performed to implant a plurality of solder balls 27 on the substrate 2, the solder balls 27 expose the packaging gel 26 and serve as the input / output terminal (InpUt / Qu ^ of the semiconductor package structure). put connection), so that the chip 24 can be electrically connected to an external device (not shown) by the solder ball 27.

533518 五、發明說明(ίο) 線、模壓、植球等製程皆屬習知,故於此不復贅述。 惟以上所述者,僅係用以說明本發明之具體實施例而 已,並非用以限定本發明之可實施範圍,舉凡熟習該項技 藝者在未脫離本發明所指示之精神與原理下所完成之一切 等效改變或修飾,仍應皆由後述之專利範圍所涵蓋。533518 V. Description of the Invention (ίο) Processes such as wire, molding, and ball planting are all known, so they will not be repeated here. However, the above are only used to illustrate specific embodiments of the present invention, and are not intended to limit the implementable scope of the present invention. For those skilled in the art, it can be completed without departing from the spirit and principles indicated by the present invention. All equivalent changes or modifications should still be covered by the scope of patents mentioned later.

16603.ptd 第15頁 533518 圖式簡單說明 [圖式簡單說明] 為讓本發明之上述及其他目的、特徵以及優點能更明 顯易懂,將與較佳實施例,並配合所附圖示,詳細說明本 發明之實施例,所附圖示之内容簡述如下·· 第1圖係本發明之基板之上視圖; 第2A及2B圖係第1圖之基板分別沿2A-2A及2B-2B線切 開之剖視圖; 第3A至3D圖係使用第2B圖基板之半導體封裝件之製程 剖面示意圖; 第4A圖係習知基板之上視圖; 第4B圖係第4A圖之基板沿4B-4B線切開之剖視圖;以 及 第4C圖係第4B圖之基板接置有晶片之剖視圖。 [元件符號說明] 1 基板 10 晶片接置區 11 金屬層 110 部位(散熱墊) 12 拒銲劑層 13 膠黏劑 14 晶片 R 區域 2 基板 20 芯層 200 上表面 201 下表面 202 晶片接置區 203 貫孔 204 散熱墊 21 金屬層 210 中心部 211 周邊部 212 連接部 213 槽孔16603.ptd Page 15 533518 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, it will be combined with the preferred embodiment and the accompanying drawings. The embodiments of the present invention are explained in detail, and the contents of the attached drawings are briefly described as follows: Figure 1 is a top view of the substrate of the present invention; Figures 2A and 2B are the substrates of Figure 1 along 2A-2A and 2B- Section 2B cut-away view; Figures 3A to 3D are schematic cross-sectional views of the semiconductor package using the substrate of Figure 2B; Figure 4A is a top view of a conventional substrate; Figure 4B is a substrate along Figure 4A along 4B-4B A cross-sectional view taken along a line; and FIG. 4C is a cross-sectional view of a substrate on which a wafer is attached in FIG. 4B. [Description of component symbols] 1 Substrate 10 Wafer contact area 11 Metal layer 110 (heat-dissipating pad) 12 Solder resist layer 13 Adhesive 14 Wafer R area 2 Substrate 20 Core layer 200 Upper surface 201 Lower surface 202 Wafer contact area 203 Through hole 204 Thermal pad 21 Metal layer 210 Central portion 211 Peripheral portion 212 Connection portion 213 Slot hole

16603.ptd 第16頁 53351816603.ptd Page 16 533518

圖式簡單說明 2 1 4 散熱墊 22 拒銲材質層 2 2 0 開孔 23 膠黏劑 2 4 晶片 25 銲線 26 封裝膠體 27 鲜球 R1 區域 R2 區域 16603.ptd 第17頁Brief description of the drawing 2 1 4 Thermal pad 22 Solder resist material layer 2 2 0 Opening hole 23 Adhesive 2 4 Chip 25 Welding wire 26 Packaging gel 27 Fresh ball R1 area R2 area 16603.ptd Page 17

Claims (1)

533518 六、申請專利範圍 1. 一種作為晶片承載件之基板,係包括: 一芯層,於其至少一表面上界定有至少一晶片接 置區; 至少一金屬層,形成於該芯層之晶片接置區上, 該金屬層具有一中心部、一圍繞該中心部之周邊部、 及多數連接該中心部與周邊部之連接部,其中,該周 邊部開設有多數貫穿該金屬層之槽孔,以使該槽孔内 之區域之芯層外露出該金屬層;以及 一拒銲材質層,敷設至該金屬層上,以使該晶片 接置區上未以該金屬層所覆蓋之區域之芯層外露出該 拒銲材質層,其中,該拒銲材質層於對應至該金屬層 之中心部及連接部之預定部位上開設有多數貫穿該拒 銲材質層之開孔,以令該預定部位之中心部及連接部 之金屬層得藉該開孔而外露出該拒銲材質層。 2. 如申請專利範圍第1項之基板,其中,該芯層係以選自 環氧樹脂、聚亞醯胺樹脂、B T樹脂及F R 4樹脂所組成之 組群之一樹脂材料製成。 3 ·如申請專利範圍第1項之基板,其中,該金屬層係以銅 製成。 4. 如申請專利範圍第1項之基板,其中,該連接部係呈輻 射狀排列。 5. 如申請專利範圍第1項之基板,其中,該外露出拒銲材 質層之芯層係相鄰連接部間之區域之芯層以及外露於 該金屬層槽孔内之芯層。533518 6. Scope of patent application 1. A substrate as a wafer carrier, comprising: a core layer defining at least one wafer receiving area on at least one surface thereof; at least one metal layer formed on the wafer of the core layer On the contact area, the metal layer has a central portion, a peripheral portion surrounding the central portion, and a plurality of connecting portions connecting the central portion and the peripheral portion, wherein the peripheral portion is provided with a plurality of slot holes penetrating the metal layer. So that the core layer of the area inside the slot exposes the metal layer; and a solder resist material layer is laid on the metal layer so that the area on the wafer receiving area that is not covered by the metal layer is The core material layer exposes the solder mask material layer, wherein the solder mask material layer is provided with a plurality of openings penetrating through the solder mask material layer at predetermined positions corresponding to the central portion and the connection portion of the metal layer, so that the predetermined The metal layer of the central part of the part and the connection part may expose the solder resist material layer by the opening. 2. The substrate according to item 1 of the patent application scope, wherein the core layer is made of a resin material selected from the group consisting of epoxy resin, polyurethane resin, B T resin and F R 4 resin. 3. The substrate according to item 1 of the patent application scope, wherein the metal layer is made of copper. 4. For the substrate of the first scope of the patent application, wherein the connecting portions are arranged in a radial pattern. 5. For the substrate of the scope of patent application No. 1, wherein the core layer exposing the solder resist material layer is the core layer in the area between adjacent connection portions and the core layer exposed in the slot of the metal layer. 16603.ptd 第18頁 533518 六、申請專利範圍 6 ·如申請專利範 部之外露部位 區上之晶片得 7.如申請專利範 以拒銲劑構成 8. —種以 金屬層 開設有 接該中 之芯層 材質層 區域之 層於對 位之中 拫銲材 一一 、外露 ;^金屬 基板為 基板, ,該金 多數貫 心部與 外露出 ,而令 芯層外 應至該 多數貫 心部及 質層; 膠黏劑 出該拒 層; 曰曰 片 區上; 多數導電 圍第1項之基板,其中,該中心部及 係作為散熱塾,以令接置於該晶片接置接 藉,散熱塾而散逸熱量至外界。接置 圍第1項之基板,其中,該拒銲材質層係 晶片承載件夕、上、g 干之+導體封裝件,係包 芯層之晶片接置區上形成有 . 屬層具有-中心部、一圍繞該中心;; 周邊部之連孔之周邊部、及多數連 該金屬層,;:厲以使該槽孔内之區域 該晶片接置°區::層上並ΐ設有1銲 露出該拒銲材G以=屬=蓋之 金屬層之中心1^ ^ 以巨鋅材質 該拒銲材質層之開:,以令 連接部之金屬層得藉該開孔而外露出;; ’敷設至兮曰μ上占 銲材質; 置區上之拒銲材質層 之芯層及外露出該拒銲材質層 二4膠黏劑而黏接於該基板之晶片接置 元件,用以電性連接該晶片至該基板上 :以及16603.ptd Page 18 533518 6. Scope of patent application 6 · If the wafer on the exposed area of the patent application scope is obtained 7. If the patent application scope is composed of solder resist 8. A kind of metal layer is provided to connect to the The layer of the core material layer area is in the alignment, the welding material is exposed one by one; ^ The metal substrate is the substrate, and the majority of the gold cores are exposed to the outside, so that the core layer should be outside the majority of the cores and the cores. The adhesive layer is on the refractory layer; on the area; most of the substrates of the conductive enveloping item 1, wherein the central part and the heat sink are used as heat sinks, so that the chips can be placed on the chip and borrowed to dissipate heat. And dissipate heat to the outside world. The substrate surrounding the first item, wherein the solder resist material layer is a wafer carrier, an upper, a g + conductor package, and is formed on a wafer receiving area of a core layer. The layer has a center The peripheral part of the peripheral part, and the peripheral part of the hole, and the majority connected to the metal layer ;: so that the area within the slot is connected to the wafer ° area :: 1 is provided on the layer Welding exposes the welding-rejection material G to = belongs to the center of the metal layer of the cover 1 ^ ^ The material of the welding-resistance material layer is opened with a giant zinc material: so that the metal layer of the connection portion can be exposed through the opening; 'Lay it to the top and bottom of μ to account for the solder material; the core layer of the solder mask material layer on the placement area and the wafer bonding component exposed to the solder mask material layer 2 and 4 on the substrate for electrical connection Connect the chip to the substrate: and 533518 六、申請專利範圍 一封裝膠體,與該基板結合用以包覆該晶片。 9.如申請專利範圍第8項之半導體封裝件,其中,該芯層 係以選自環氧樹脂、聚亞醯胺樹脂、BT樹脂及FR4樹脂 所組成之組群之一樹脂材料製成。 1 0 .如申請專利範圍第8項之半導體封裝件,其中,該金屬 層係以銅製成。 1 1 .如申請專利範圍第8項之半導體封裝件,其中,該連接 部係呈輻射狀排列。 1 2 .如申請專利範圍第8項之半導體封裝件,其中,該外露 出拒銲材質層之芯層係相鄰連接部間之區域之芯層以 及外露於該金屬層槽孔内之芯層。 1 3.如申請專利範圍第8項之半導體封裝件,其中,該中心 部及連接部之外露部位係作為散熱墊,以令該晶片得 藉該散熱塾而散逸熱量至外界。 1 4 .如申請專利範圍第8項之半導體封裝件,其中,該拒銲 材質層係以拒銲劑構成。 1 5 _如申請專利範圍第8項之半導體封裝件,其中,該膠黏 劑係銀膠。 1 6 .如申請專利範圍第8項之半導體封裝件,其中,該敷設 至外露芯層上之膠黏劑得與該芯層緊密結合而不會溢 膠至該晶片接置區外。 1 7.如申請專利範圍第8項之半導體封裝件,其中,該導電 元件係銲線。 1 8 ·如申請專利範圍第8項之半導體封裝件,其中,該封裝533518 VI. Scope of patent application A packaging gel is combined with the substrate to cover the wafer. 9. The semiconductor package of claim 8 in which the core layer is made of a resin material selected from the group consisting of epoxy resin, polyurethane resin, BT resin, and FR4 resin. 10. The semiconductor package of claim 8 in which the metal layer is made of copper. 1 1. The semiconductor package according to item 8 of the patent application, wherein the connection portions are arranged in a radial pattern. 1 2. The semiconductor package according to item 8 of the scope of patent application, wherein the core layer exposing the solder resist material layer is a core layer in a region between adjacent connection portions and a core layer exposed in a slot of the metal layer . 1 3. The semiconductor package according to item 8 of the patent application scope, wherein the exposed portion of the central portion and the connecting portion is used as a heat dissipation pad, so that the chip can dissipate heat to the outside by the heat sink. 14. The semiconductor package according to item 8 of the scope of patent application, wherein the solder resist material layer is made of a solder resist. 1 5 _ If the semiconductor package of item 8 of the patent application, wherein the adhesive is a silver paste. 16. The semiconductor package according to item 8 of the scope of patent application, wherein the adhesive applied to the exposed core layer can be tightly combined with the core layer without overflowing the adhesive outside the wafer receiving area. 1 7. The semiconductor package of claim 8 in which the conductive element is a bonding wire. 1 8 · The semiconductor package of item 8 in the scope of patent application, wherein the package 16603.ptd 第20頁 53351816603.ptd Page 20 533518 16603.ptd 第21頁16603.ptd Page 21
TW091110599A 2002-05-21 2002-05-21 Substrate for carrying chip and semiconductor package having the same TW533518B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW091110599A TW533518B (en) 2002-05-21 2002-05-21 Substrate for carrying chip and semiconductor package having the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091110599A TW533518B (en) 2002-05-21 2002-05-21 Substrate for carrying chip and semiconductor package having the same

Publications (1)

Publication Number Publication Date
TW533518B true TW533518B (en) 2003-05-21

Family

ID=28788685

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091110599A TW533518B (en) 2002-05-21 2002-05-21 Substrate for carrying chip and semiconductor package having the same

Country Status (1)

Country Link
TW (1) TW533518B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392845C (en) * 2004-11-12 2008-06-04 日月光半导体制造股份有限公司 Packaging structure with high adhesiveness between substrate and packaging colloid

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100392845C (en) * 2004-11-12 2008-06-04 日月光半导体制造股份有限公司 Packaging structure with high adhesiveness between substrate and packaging colloid

Similar Documents

Publication Publication Date Title
US6515361B2 (en) Cavity down ball grid array (CD BGA) package
JP3578770B2 (en) Semiconductor device
TWI253155B (en) Thermally enhanced semiconductor package and fabrication method thereof
TWI529878B (en) Hybrid thermal interface material for ic packages with integrated heat spreader
JP5227501B2 (en) Stack die package and method of manufacturing the same
JP2001284523A (en) Semiconductor package
TW200416787A (en) Semiconductor stacked multi-package module having inverted second package
KR100698526B1 (en) A wiring board having a heat dissipation layer and a semiconductor package using the same
TW565918B (en) Semiconductor package with heat sink
CN101877334B (en) Semiconductor device with thermal gain
US6819565B2 (en) Cavity-down ball grid array semiconductor package with heat spreader
TW200828527A (en) Chip package and method of manufacturing the same
US7157292B2 (en) Leadframe for a multi-chip package and method for manufacturing the same
US7101733B2 (en) Leadframe with a chip pad for two-sided stacking and method for manufacturing the same
JPH10335577A (en) Semiconductor device and its manufacture
TW533518B (en) Substrate for carrying chip and semiconductor package having the same
CN100411121C (en) Heat dissipation type package structure and manufacturing method thereof
JP3628991B2 (en) Semiconductor device and manufacturing method thereof
JP2003060155A (en) Semiconductor package and its manufacturing method
TW200522298A (en) Chip assembly package
TW200941658A (en) Semiconductor device with enhanced heat dissipation effect
CN102254880B (en) Chip packaging device and manufacturing method thereof
KR100473336B1 (en) semiconductor package
JPH0358455A (en) Semiconductor package
TWI297538B (en) Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent