TW533518B - Substrate for carrying chip and semiconductor package having the same - Google Patents

Abstract

A substrate for carrying a chip is provided, which includes a core layer defined with a chip attach area on which at least one metallic layer is formed. The metallic layer is of a central portion, a peripheral portion surrounding the central portion and formed with a plurality of vias, and a plurality of bridging portions for interconnecting the central portion and the peripheral portion. A solder mask layer is applied over the metallic layer, which leaves the chip attach area of the core layer uncovered by the metallic layer to be exposed to the solder mask layer. A plurality of openings are formed in the solder mask layer so as to expose the metallic layer connecting the openings. By exposing the chip attach area of the core layer uncovered by the metallic layer to the solder mask layer, the adhesive applied to the chip attach area for adhering a chip to the substrate can be in direct contact with the core layer. It thus enhances the reliability and quality of packages thus obtained.

Description

533518 V. Description of the invention (1) [Field of the invention] The present invention relates to a substrate, particularly a substrate suitable for a semiconductor package and used as a wafer carrier, and a semiconductor package using the substrate. [Background Description] A conventional substrate for a Ball Grid Array (BGA) semiconductor package is a metal layer (usually a copper layer) formed on a chip attach area of the substrate, and A solder mask layer is laid on the substrate, and the solder mask layer is provided with a plurality of openings, so that a predetermined portion of the metal layer can expose the solder mask layer by the openings. Then, an adhesive (Adhesive) is applied on the solder resist layer and the exposed metal layer of the wafer receiving area, and a wafer is adhered to the substrate by the adhesive. However, this design has many disadvantages. First, the above metal layer completely covers the wafer interface area, so that the solder resist layer applied to the wafer interface area can only be attached to the metal layer; due to the adhesion of the solder resist to the metal Poor sex, so prone to problems such as delamination (Del ami nation). In addition, the adhesive applied to the wafer receiving area is only in contact with the solder resist layer and the metal layer. Due to the poor adhesion of the adhesive to the metal, it is easy to delaminate between the adhesive and the metal layer, and further Delamination spreading between the adhesive and the solder resist layer also caused serious damage to the adhesion between the chip and the substrate. In view of this, U.S. Patent Nos. 5,703,402, 5,216,478 and 5,409,863 developed another substrate 1 for BGA semiconductor packages, as shown in Figures 4A and 4B. 'Characterized by the wafer connection of the substrate 1 The placement region 10 forms a metal layer 1 in a Sun Ray manner so that part of the crystal

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The wafer-receiving region 10 is not covered by the metal layer 11 (that is, the region R of the wafer-receiving region 10). A solder resist layer 12 is laid on the substrate 1, and the solder resist layer 12 is provided with a plurality of openings 120 so that the metal layer at a predetermined portion 110 is exposed to the solder resist layer 12; the metal layer 1 The exposed part i 丨 〇 is used as a thermal pad, so that subsequent wafers (not shown) carried on the wafer receiving area 10 can use the heat dissipation pad to dissipate heat to the outside. Such a radial metal layer 11 enables the solder resist layer 12 to be directly attached to the wafer receiving area. The area R that is not covered with the metal layer 1 1 enhances the tinting resist layer 1 2 and the spotted substrate 1 Binding force 'to improve delamination caused by poor adhesion. However, as shown in FIG. 4C, the above-mentioned substrate i is used for the die-bonding operation. When an adhesive 13 is applied to the wafer receiving area 10 for bonding the wafer ^ 4, the adhesive 1 3 Adhering only to the solder resist layer 2 and the metal layer n cannot solve the shortcomings such as insufficient bonding force between the adhesive and the substrate, and easy to cause delamination; meanwhile, the adhesive with poor adhesion also easily leads to the uneven distribution of the adhesive This can cause problems such as overflowing glue outside the wafer receiving area, and forming voids at the corners of the wafer. In subsequent high-temperature processes, there is a popcorn phenomenon that can easily occur. Damage the quality and yield of finished products. In addition, the number of exposed portions (heat-dissipating pads) 11 of the metal layer 11 is insufficient to efficiently dissipate heat generated from the operation of the chip 14 to the outside, which may affect the reliability of the finished product due to overheating. Therefore, how to develop a substrate that can effectively improve the bonding force between the adhesive and the substrate 'and improve the heat dissipation efficiency of the chip is a subject that must be discussed. [Invention Overview]

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One aspect of the present invention and the use of the bonding force between the semi-layout of the substrate and the core layer of the substrate, and controlling the quality of the finished product, is to provide a conductor package, which can be used on the core layer to make adhesive. Agent overflow, distribution reliability. The substrate of the wafer carrier · The adhesive used can directly improve the unevenness of the adhesive and the substrate, and it is sure to provide ^^ for making hair θ T is the base member of the wafer carrier 'set plate β evening Counting more than one thermal pad operation results in 3 ^ King of Heat I. Another improvement of the present invention is to lift the board and use the substrate's semiconductor package (Thermal Pad) to effectively dissipate the heat dissipation efficiency of the overall package structure of the chip. . In order to achieve the above disclosure and other purposes, the present invention discloses a substrate of a carrier and a semiconductor package using the substrate. The A plate includes: a core layer, at least one surface of which is defined with at least: two chip attachment areas (Chip Attach Area), at least one metal layer formed on the wafer interface area of the core layer, The metal layer has a central portion, a peripheral portion surrounding the central portion, and a plurality of connecting portions connecting the central portion and the peripheral portion, wherein the peripheral portion is provided with a plurality of slot holes penetrating the metal layer to make the slot The metal layer is exposed from the core layer in the area inside the hole; and a Solder Mask layer is laid on the metal layer so that the core layer in the area where the wafer is not covered by the metal layer (That is, the core layer in the area between adjacent connection portions and the core layer exposed in the slot of the metal layer) the solder resist layer is exposed, wherein the solder resist layer corresponds to the center portion and the connection portion corresponding to the metal layer The predetermined portion is provided with a plurality of openings penetrating through the solder resist layer, so that the metal layer of the center portion and the connection portion of the predetermined portion is exposed to the solder resist layer and serves as a heat dissipation pad, so as to be placed on the wafer. Wafers on the contact area

16603, ptd page 8 533518 V. Description of the invention (4) Dissipate heat to the outside world through the heat sink. The semiconductor package structure using the above substrate is an adhesive (such as silver paste) is applied to a solder resist layer on a wafer receiving area, a core layer exposing the solder resist layer, and the solder resist layer is exposed. Metal layer · Then, by using the adhesive, a wafer is adhered to the wafer receiving area of the substrate, and then processes such as wire bonding, molding, and implantation are performed. The semiconductor package of the present invention is completed. Because the adhesion between the adhesive and the core layer of the resin material is better than the adhesion between the adhesive and the solder resist, the area covered by the solder layer on the wafer contact area is greatly reduced, and part of the core layer ( (Such as the core layer in the area between adjacent connection parts) is exposed to directly adhere to the adhesive, which can effectively improve the bonding force between the adhesive and the substrate, and eliminate conventional adhesives and soldering fluxes. It has poor adhesion and may cause defects such as delamination. At the same time, the periphery of the metal layer is provided with a large number of slots, and the core layer in the area of the slot is also exposed with a solder resist layer to directly bond with the adhesive, in addition to further increasing the bonding force between the adhesive and the substrate In addition to its effectiveness, the compound can effectively control the overflow of the adhesive, so that the adhesive does not overflow outside the wafer receiving area and cause problems such as improper overflow and creeping, to ensure the quality of the sticking operation. Therefore, the direct contact area between the adhesive and the core layer is greatly increased, and the problems such as uneven distribution of the adhesive and the formation of air holes (Vo id) in the corners of the wafer can be improved to avoid popcorn caused by air holes. To ensure the structural integrity of the substrate and wafer and the yield of the finished product. In addition, compared with the conventional substrate in which only a small number of heat dissipation pads are formed on the center portion of the metal layer, the metal layer of the present invention is provided on the center portion and the connection portion at the same time.

ϋΙΙΗΙ 16603.ptd Page 9 533518 V. Description of the invention (5) The heat dissipation pads are arranged and the number of heat dissipation pads is greatly increased, so the heat dissipation efficiency can be effectively improved, and the heat generated by the chip operation can be efficiently dissipated to the outside world, Do not affect the reliability of the finished product due to overheating. [Detailed description of the invention] The following is a detailed description of the substrate disclosed by the present invention and the semiconductor package using the same in conjunction with the attached drawings 1 to 3, but these drawings are simplified diagrams. The structural units related to the present invention are shown, and these structural units are not drawn according to the actual number or size ratio, and the actual structural layout of the substrate and the semiconductor package should be more complicated. Figures 1, 2 A and 2 B are respectively a top view and a cross-sectional view of the substrate 2 of the present invention. As shown in the figure, the substrate 2 includes: a Co layer 20; at least one metal layer 21 formed on a chip attach area 202 of the core layer 20; and a resist layer The solder material layer 22 is laid on the metal layer 20 so that a wafer (not shown) can be carried on the wafer receiving area 202 in a subsequent process. First, the "layer 20" is prepared. The core layer 20 is made of a resin material for conventional substrates, such as an oxygen resin (Ep 0x y Resin), a polyimide resin, a βT resin, or a FR4 resin. Therefore, the manufacturing method of the core layer will not be described in detail here. The core layer 20 has an upper surface 200 and a relatively lower surface 201; the upper surface 200 defines at least one wafer receiving area 202, which is used for subsequent die bonding; the wafer receiving area A plurality of via holes (Via) 203 which penetrate through the core layer 20 are provided in the 002, and the via holes 203 are used as thermal vias (Thermal Vias) (described later in detail). ",,

16603.ptd Page 10 533518 V. Description of the invention (6) Then, a predetermined circuit layout such as a conductive trace (not shown) is formed on the core layer 20 and the lower surface 2 0, 201. A metal layer (such as copper, etc.) 21 is arranged on the wafer receiving area 202 of the core layer 20, and a thermally conductive metal (such as copper, etc.) is plated on the inner wall of the through hole, so that the thermal energy or heat is obtained from the The metal layer 21 is conducted to the thermal pad 204 disposed on the lower surface 201 of the core layer 20 through the through hole 203. The conductive trace, the metal layer 21 and the heat dissipation pad 204 are manufactured by laminating copper foils (not shown) on the upper and lower surfaces 200 and 201 of the core layer 20 with conventional exposure (Exposing), Development (Etching) and other operations to pattern it to form a predetermined circuit layout; this manufacturing method is known, so it will not be repeated here. The metal layer 21 on the wafer receiving area 202 of the angry layer 20 has a central portion 2 1 0, a peripheral portion 2 1 1 surrounding the central portion 2 1 0, and a plurality of connecting portions between the central portion 210 and the peripheral portion 211. The connection portion 212; the function of the metal layer 21 is to electrically and thermally communicate with a wafer (not shown) subsequently mounted on the wafer receiving area 202. Due to the poor adhesion between the copper metal layer 21 and the resin material of the core layer 20, the metal layer 21 adopts a Sun Ray design, that is, the connection portion 2 of the metal layer 21;! 2 They are arranged in a similar light-like manner, as shown in FIG. 1 (the number of the connecting portions 212 is not limited to those shown in the figure). In this way, the wafer is connected, and the core layer of the area 201 that is not covered by the metal layer 21, that is, the core layer 20 of the region R1 between the photo-connecting sections 2 12 is exposed, and the metal layer is exposed at the same time. The balance between adhesion and thermal conductivity (or heat dissipation) effect, the size of the metal layer 21 needs to be moderate; if the metal layer 21 is too small, it will affect heat dissipation

533518 V Description of the invention (7) Effect; if the metal layer 21 is too large, it will lead to poor adhesion, and it will easily cause delamination between the metal layer 21 and the core layer 20 (Del ami nation). Since the design of the radial or radiant metal layer 21 is conventional, it will not be repeated here. Furthermore, the peripheral portion 211 of the metal layer 21 is provided with a plurality of slot holes 2 1 3 penetrating through the metal layer 21 so that the core layer 2 of the region R 2 within the slot hole 2 1 3 exposes the metal layer 21. . Finally, a solder resist material layer 22, such as a solder resist (f mask), is laid on the core layer 20 above, the lower surface 20 {), and 201 to cover the core layer 20. The circuit layout prevents the conductive traces from being air-tightly isolated from the outside by forming a protective layer, which protects them from the risk of being oxidized or subject to external forces and contaminants. Selectively (S e 1 ective) remove a part of the solder resist material layer 22 so that the heat radiation pad 204 on the lower surface 201 of the core layer 20 exposes the solder resist material layer 22 and make the applied β To date, the solder-repellent material layer 22 on the wafer receiving area 202 only covers the metal layer 20, and the core layer 20 on the wafer receiving area 202 is not covered by the metal layer 21 That is, the core layer 20 in the area r 丨 between the adjacent connection portions 2 1 2 and the core layer 2 fU FB R2 exposed in the peripheral portion 2 1 1 slot 2 1 3), the anti-front material layer is exposed. twenty two. In addition, the solder resist material layer 22 is provided with a plurality of openings 22 0 penetrating through the solder resist material layer 2 2, and the opening holes 22 0 correspond to the central portion 2 of the metal layer 21. And a predetermined portion on the connection portion 2 1 2 so that the center portion 20 of the predetermined portion and the metal layer 21 of the connection portion 2 12 may expose the fresh-repellent material layer 22 through the opening 220. The The exposed metal layers / parts of the central portion 210 and the connecting portion 212 are used as heat dissipation pads 214 'to allow subsequent placement on the wafer receiving area 2Q2.

533518 V. Description of the invention (8) The heat generated by the operation of the tablet (not shown) can be dissipated to the outside through the heat dissipation pad 214, the heat dissipation through hole 203, and the heat dissipation pad 204. Compared with the conventional substrate, only a small number of heat radiation pads are formed on the center portion of the metal layer, the metal layer 21 of the present invention is provided with a heat radiation pad 2 on the center portion 2 10 and the connection portion 2 12 at the same time. And the number of heat sink pads 204 is greatly increased, so the heat dissipation effect can be effectively improved, and the heat generated by the chip operation can be efficiently dissipated to the outside without affecting the reliability of the finished product due to overheating.

3A to 3D are schematic diagrams showing a manufacturing process of a semiconductor package using the above-mentioned substrate 2. The following description only uses a ball grid array (Bali GHd Array, BGA) package as an example, but the scope of the present invention is not limited thereto. First, as shown in FIG. 3A, a substrate 2 is prepared, and an adhesive 23 such as Silver Paste is applied on the wafer receiving area 202 of the substrate 2 to coat the adhesive 23. A solder resist material layer 22 on the wafer receiving area 202, a core layer 20 on which the solder resist material layer 22 is exposed, and a metal layer 21 on which the solder resist material layer 22 is exposed.

Because the adhesiveness between the adhesive 23 and the core layer 20 (resin material) is excellent} The adhesiveness between the adhesive 23 and the solder resist material layer (solder resist) 22, therefore, the width of the wafer receiving area is reduced 2 The area covered by the solder-resistant material layer 22 on 02, = make part = core layer 20 (for example, the core layer $ in the area between adjacent connection parts 212 is not exposed) is exposed to directly adhere to the adhesive 23 The effective joint force between J m ^ m and the substrate 2 is to eliminate the shortcomings of the conventional technology, such as poor adhesion, which may cause delamination, etc., and the peripheral part of the slot 2 1 3 2 11 is provided with a plurality of slot holes 2 1 3, and the core layer 20 of the product domain R2 is also exposed to the solder resist material layer 22

16603.ptd Page 13 533518 V. Description of the invention (9) Adhesion directly to the adhesive 2 3, in addition to further increasing the effect of the adhesion and synergy between the adhesive 2 3 and the substrate 2, the compound can effectively control the adhesive 2 3 The overflowing glue condition prevents the adhesive 23 from overflowing outside the wafer receiving area 2 02 and causing problems such as improper overflowing and creeping, to ensure the quality of the sticking operation. Therefore, the area of direct contact between the adhesive 23 and the core layer 20 is greatly increased, and the problems of uneven distribution of the adhesive and the formation of air holes (V oid) in the corners of the wafer can be improved to avoid the gas caused by the air holes. Popcorn phenomenon, to ensure the structural integrity and yield of finished products. Then, as shown in FIG. 3B, a die bonding operation is performed, and a wafer 24 is bonded to the wafer receiving area 202 of the substrate 2 by the adhesive 23, and then, as shown in FIG. 3C As shown, a wire bonding operation is performed, and a plurality of bonding wires 25 are soldered to the wafer 24 and the substrate 2, so that the wafer 24 is electrically connected to the substrate 2. Finally, as shown in FIG. 3D, a molding operation is performed to form an encapsulant 26 from a resin compound (such as epoxy resin). The encapsulant 26 is combined with the substrate 2 to cover and carry the substrate 2. The wafer 24 and the bonding wire 25 on the wafer 24 and the bonding wire 25 are separated from the outside air, so as not to be affected by external impact (Ifflpact) or pollutants. Then, an “implantation” operation is performed to implant a plurality of solder balls 27 on the substrate 2, the solder balls 27 expose the packaging gel 26 and serve as the input / output terminal (InpUt / Qu ^ of the semiconductor package structure). put connection), so that the chip 24 can be electrically connected to an external device (not shown) by the solder ball 27.

533518 V. Description of the Invention (ίο) Processes such as wire, molding, and ball planting are all known, so they will not be repeated here. However, the above are only used to illustrate specific embodiments of the present invention, and are not intended to limit the implementable scope of the present invention. For those skilled in the art, it can be completed without departing from the spirit and principles indicated by the present invention. All equivalent changes or modifications should still be covered by the scope of patents mentioned later.

16603.ptd Page 15 533518 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, it will be combined with the preferred embodiment and the accompanying drawings. The embodiments of the present invention are explained in detail, and the contents of the attached drawings are briefly described as follows: Figure 1 is a top view of the substrate of the present invention; Figures 2A and 2B are the substrates of Figure 1 along 2A-2A and 2B- Section 2B cut-away view; Figures 3A to 3D are schematic cross-sectional views of the semiconductor package using the substrate of Figure 2B; Figure 4A is a top view of a conventional substrate; Figure 4B is a substrate along Figure 4A along 4B-4B A cross-sectional view taken along a line; and FIG. 4C is a cross-sectional view of a substrate on which a wafer is attached in FIG. 4B. [Description of component symbols] 1 Substrate 10 Wafer contact area 11 Metal layer 110 (heat-dissipating pad) 12 Solder resist layer 13 Adhesive 14 Wafer R area 2 Substrate 20 Core layer 200 Upper surface 201 Lower surface 202 Wafer contact area 203 Through hole 204 Thermal pad 21 Metal layer 210 Central portion 211 Peripheral portion 212 Connection portion 213 Slot hole

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Brief description of the drawing 2 1 4 Thermal pad 22 Solder resist material layer 2 2 0 Opening hole 23 Adhesive 2 4 Chip 25 Welding wire 26 Packaging gel 27 Fresh ball R1 area R2 area 16603.ptd Page 17

Claims (1)

533518 6. Scope of patent application 1. A substrate as a wafer carrier, comprising: a core layer defining at least one wafer receiving area on at least one surface thereof; at least one metal layer formed on the wafer of the core layer On the contact area, the metal layer has a central portion, a peripheral portion surrounding the central portion, and a plurality of connecting portions connecting the central portion and the peripheral portion, wherein the peripheral portion is provided with a plurality of slot holes penetrating the metal layer. So that the core layer of the area inside the slot exposes the metal layer; and a solder resist material layer is laid on the metal layer so that the area on the wafer receiving area that is not covered by the metal layer is The core material layer exposes the solder mask material layer, wherein the solder mask material layer is provided with a plurality of openings penetrating through the solder mask material layer at predetermined positions corresponding to the central portion and the connection portion of the metal layer, so that the predetermined The metal layer of the central part of the part and the connection part may expose the solder resist material layer by the opening. 2. The substrate according to item 1 of the patent application scope, wherein the core layer is made of a resin material selected from the group consisting of epoxy resin, polyurethane resin, B T resin and F R 4 resin. 3. The substrate according to item 1 of the patent application scope, wherein the metal layer is made of copper. 4. For the substrate of the first scope of the patent application, wherein the connecting portions are arranged in a radial pattern. 5. For the substrate of the scope of patent application No. 1, wherein the core layer exposing the solder resist material layer is the core layer in the area between adjacent connection portions and the core layer exposed in the slot of the metal layer. 16603.ptd Page 18 533518 6. Scope of patent application 6 · If the wafer on the exposed area of the patent application scope is obtained 7. If the patent application scope is composed of solder resist 8. A kind of metal layer is provided to connect to the The layer of the core material layer area is in the alignment, the welding material is exposed one by one; ^ The metal substrate is the substrate, and the majority of the gold cores are exposed to the outside, so that the core layer should be outside the majority of the cores and the cores. The adhesive layer is on the refractory layer; on the area; most of the substrates of the conductive enveloping item 1, wherein the central part and the heat sink are used as heat sinks, so that the chips can be placed on the chip and borrowed to dissipate heat. And dissipate heat to the outside world. The substrate surrounding the first item, wherein the solder resist material layer is a wafer carrier, an upper, a g + conductor package, and is formed on a wafer receiving area of a core layer. The layer has a center The peripheral part of the peripheral part, and the peripheral part of the hole, and the majority connected to the metal layer ;: so that the area within the slot is connected to the wafer ° area :: 1 is provided on the layer Welding exposes the welding-rejection material G to = belongs to the center of the metal layer of the cover 1 ^ ^ The material of the welding-resistance material layer is opened with a giant zinc material: so that the metal layer of the connection portion can be exposed through the opening; 'Lay it to the top and bottom of μ to account for the solder material; the core layer of the solder mask material layer on the placement area and the wafer bonding component exposed to the solder mask material layer 2 and 4 on the substrate for electrical connection Connect the chip to the substrate: and 533518 VI. Scope of patent application A packaging gel is combined with the substrate to cover the wafer. 9. The semiconductor package of claim 8 in which the core layer is made of a resin material selected from the group consisting of epoxy resin, polyurethane resin, BT resin, and FR4 resin. 10. The semiconductor package of claim 8 in which the metal layer is made of copper. 1 1. The semiconductor package according to item 8 of the patent application, wherein the connection portions are arranged in a radial pattern. 1 2. The semiconductor package according to item 8 of the scope of patent application, wherein the core layer exposing the solder resist material layer is a core layer in a region between adjacent connection portions and a core layer exposed in a slot of the metal layer . 1 3. The semiconductor package according to item 8 of the patent application scope, wherein the exposed portion of the central portion and the connecting portion is used as a heat dissipation pad, so that the chip can dissipate heat to the outside by the heat sink. 14. The semiconductor package according to item 8 of the scope of patent application, wherein the solder resist material layer is made of a solder resist. 1 5 _ If the semiconductor package of item 8 of the patent application, wherein the adhesive is a silver paste. 16. The semiconductor package according to item 8 of the scope of patent application, wherein the adhesive applied to the exposed core layer can be tightly combined with the core layer without overflowing the adhesive outside the wafer receiving area. 1 7. The semiconductor package of claim 8 in which the conductive element is a bonding wire. 1 8 · The semiconductor package of item 8 in the scope of patent application, wherein the package 16603.ptd Page 20 533518 16603.ptd Page 21