544932 A7 B7 五、發明説明（1 ) 【發明領域】 (請先閲讀背面之注意事項再填寫本頁) 本發明係關於具有金屬（M)-氧化膜（0)-半導體膜（S)的閘 極構造之MOS型場效電晶體（以下記爲MOSFET)、絕緣閘 極雙載子電晶體（以下記爲IGBT)等的半導體裝置，特別是 關於電流流過配設在半導體基板兩面的電極間的縱型高耐 壓、低損失的半導體裝置。 【發明背景】 【習知技藝之說明】 一般對於功率（Power)半導體元件，常用電流流過配設 在半導體基板兩面的電極間的縱型半導體。圖36係習知的 平面（Planar)型的η通道（Channel)縱型MOSFET的一例的主 電流流過的主動部的剖面圖。 經濟部智慧財產局員工消費合作社印製 此縱型MOSFET在汲電極20所導電接合的低電阻的n + 汲極層11之上配置成爲電壓支持層的高電阻率（Specific resistivity)的n_漂移層12，在該n_漂移層12之上選擇性地配 置P井區域1 3，在該p井區域1 3內部的表面層選擇性地形 成η+源極區域1 5。 在夾在η +源極區域15與ιΓ漂移層12的表面露出部分14( 以下稱爲rT表面區域）的ρ井區域1 3的表面上，中介閘極絕 緣膜17配設閘電極18，在n+源極區域15與p井區域13的表 面共通地接觸配設源電極19。 在與上述裝置（Device)內的ρ井區域13的源電極19接觸 的表面爲了降低與源電極19的接觸電阻，或閉鎖（Latch up) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 4 544932 A7 B7 五、發明説明（2 ) 耐量的提高，也有配設P +接觸（Contact)區域21的情形。 (請先閲讀背面之注意事項再填寫本頁) 若將圖36的MOSFET的汲電極20所導電接合的n +汲極 層1 1變更成低電阻的P +汲極層的話，變成平面型的n通道 縱型IGBT。此時，由成爲其上的電壓支持層的高電阻率的 ιΓ漂移層12起，上面爲與圖36的M0SFET完全相同的構成也 可以。 IGBT的動作其藉由給閘電極的訊號控制由汲電極流到 源電極的電流，此點相同，惟相對於M0SFET爲單載子 (Unipolar)型的元件，IGBT爲雙載子（Bipolar)型的元件，流 過電流時（接通（ON)狀態）的電壓下降變小。 在這種縱型M0SFET或IGB中的接通狀態下的接通電 阻（=電壓下降/電流）可以元件內部的電流路徑的電阻總和來 表示，惟特別是在高耐壓元件的接通電阻，高電阻率的^ 漂移層1 2部分的電阻成爲支配性的。 經濟部智慧財產局員工消費合作社印製 - ---- 爲了降低M0SFET或IGBT的損失或降低此ιΓ漂移層12 的電阻率，減少厚度等爲有效。但是因在斷開（OFF)狀態時 此n_漂移層12空乏化變成耐壓支持層，故爲了降低電阻値 ，提高ιΓ漂移層12的雜質濃度、降低電阻率、減少厚度等 的話會引起耐壓降低。 相反地，因耐壓高的半導體裝置必須增加η_漂移層12 的厚度，必然地接通電阻升高、損失變大。 即在接通電阻與耐壓之間有取捨（Trade-off)關係。此取 捨關係不僅M0SFET或IGBT，即使在雙載子電晶體、二極 體等的功率半導體元件中，已知有程度的差也同樣地成立 ---- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 544932 A7 B7 五、發明説明（3 ) 〇 (請先閲讀背面之注意事項再填寫本頁) 而且，如習知的上述裝置（Device)的p井區域13—般因 係以閘電極層18爲罩幕（Mask)導入雜質而形成，故其平面形 狀大致成爲閘電極層18的反轉形狀。圖37、圖38係顯示習 知裝置（Device)的閘電極18的圖案（Patterη)的例子之俯視圖 〇 圖37係閘電極1 8的開窗形狀爲四角形的例子，揭示於 日本特公平7- 831 23號公報等。ρ井區域13因藉由通過閘電 極18的窗之雜質導入而形成，故其平面形狀成爲四角形。η + 源極區域1 5係藉由以閘電極1 8的窗爲一方的端的雜質導入 而形成四角環狀。在圖37的閘電極1 8的窗內部顯示ρ井區 域13以及與η+源極區域接觸而配設的源電極的接觸區域24 。源電極接觸區域24也被製作成相似的四角形。 圖38係閘電極18的開窗形狀爲六角形的例子，揭示於 例如USP 4,593,302等。這種情形ρ井區域13的平面形狀成 爲六角形。源電極接觸區域24也被製作成相似的六角形。 經濟部智慧財產局員工消賓合作Ti印製 另一方面，關於負擔MOS型半導體裝置的耐壓之耐壓 構造，一般在主動區域（Active area)的周圍配設護環（Guard ring)構造或場電極（Field plate)構造或電阻性膜+場電極構造 等。 【發明槪要】 但是，一般的耐壓只能實現由任何耐壓構造的情形也 使用的半導體基板以及耐壓構造計算的理想耐壓的90%以下 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 544932 A7 B7 五、發明説明（4 ) 的値。 (請先閱讀背面之注意事項再填寫本頁) 因此，對於實現當作目標的耐壓，需增加半導體基板 的厚度或使用具有餘裕度的耐壓構造，即使在被要求低接 通電阻的裝置（Device)中，也無法避免接通電阻的增大。 僅能實現由構造計算的耐壓的大約90%以下的値之理由 之一爲主動（Active)部的平面的配置方法有問題，另一爲耐 壓構造部未被最佳化，比主動部還先在耐壓構造部崩潰 (Breakdown)。分別在以下稍微詳細地說明。 首先關於主動區域，P井區域13的形狀爲如圖37、圖38 的情形，各P井區域13變成被漂移層12的n_漂移表面部14 包圍的形狀。換言之，因對n_漂移表面部14 p井區域13形 成凸型，故其間的pn接合部分的電場強度因形狀效應而變 高，變成比本來以ιΓ漂移層12與p井區域13的雜質濃度決 定的耐壓還低的耐壓。 據此，爲了確保耐壓需降低ιΓ漂移層12的雜質濃度， 如此變成更增加接通電阻的一因。 經濟部智慧財產局員工消費合作社印製 抑制藉由此ρ井區域1 3的形狀效應所造成的耐壓降低 的一個方法，例如在USP5,723,890進行將閘電極的主要部 分當作延伸於一方向的條狀的方法。 圖39係顯示其閘電極18的圖案之俯視圖。這種情形ρ 井區域13的主要部分的平面形狀也成爲條狀。接觸區域24 也被製作成條狀。 但是，在令此閘電極18爲條狀的M0SFET中並非無問 題。 子 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（5 ) (請先閱讀背面之注意事項再填寫本頁) 具有習知的四角形或六角形的窗之閘電極的情形因供 給閘電極的控制訊號，其閘電極的形狀係網路（Network)地 作用，故其聞電阻（Gate resistance)被抑制於低値。但是， 令閘電極1 8爲條狀的情形因供給閘電極的控制訊號僅自條 的兩端有一方向路徑，故閘電阻增加招致後述的開關損失 (Switching loss)的增大。 對於MOSFET的損失降低需要先前所述的接通電阻所 造成的接通狀態的損失降低，並且開關時的損失降低。一 般對於開關時的損失降低，開關時間的縮短特別是縮短元 件由接通狀態變成斷開（Off)狀態時的開關時間很重要。 爲了縮短縱型MOSFET的開關時間，需要降低圖36的 表面區域14與中介閘極絕緣膜17而對向的閘電極18之間所 構成的電容Crss。而且，縮小被夾在ρ井區域13的η_表面 區域14的寬度有效。 但是若縮小被夾在ρ井區域13的ιΓ表面區域14的寬度 的話，MOSFET的接通電阻之一的因接合型場效電晶體作用 所造成的電阻成分（以下記爲JFET電阻）變大，接通電阻升 經濟部智慧財產局員工消費合作社印製 高。 此 JFET電阻升高的問題的解決法之一例如有 USP4,593,302所揭示的反摻雜（Counter dope)法。的確使用此 技術可抑制接通電阻的增加，惟因即使稍微降低JFET電阻 ，若增大11_表面區域14的寬度的話會與耐壓下降有關。對 於避免此耐壓下降，相反地需要減少反摻雜的量，其結果 有陷入減少JFET電阻的增加抑制效應之繞圈子的問題。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（6 ) (請先閱讀背面之注意事項再填寫本頁) 而且爲了開關損失的降低，除了上述Crss的降低外閘 極驅動電荷量Q g的降低也有效。Q g係以由聞極/源極間電 壓Vgs對MOS型裝置的輸入電容Ciss爲0(V)到驅動電壓 V1(V)的充電電荷量來計算，以下式表示。 [數1]544932 A7 B7 V. Description of the invention (1) [Field of invention] (Please read the notes on the back before filling out this page) The present invention relates to a gate with a metal (M) -oxide film (0) -semiconductor film (S) Semiconductor devices such as MOS field-effect transistors (hereinafter referred to as MOSFETs) and insulated-gate bipolar transistors (hereinafter referred to as IGBTs) having a polar structure, particularly regarding current flowing between electrodes arranged on both sides of a semiconductor substrate Vertical high-voltage, low-loss semiconductor device. [Background of the Invention] [Explanation of Conventional Techniques] Generally, for a power semiconductor device, a current is usually passed through a vertical semiconductor disposed between electrodes disposed on both sides of a semiconductor substrate. Fig. 36 is a cross-sectional view of an active portion through which a main current flows in an example of a conventional Planar-type n-channel vertical MOSFET. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, this vertical MOSFET is arranged on the low-resistance n + drain layer 11 conductively joined by the drain electrode 20 to be a high resistivity (specific resistivity) n_ drift of the voltage support layer. A layer 12, a P-well region 13 is selectively disposed on the n_drift layer 12, and a surface layer inside the p-well region 13 selectively forms an η + source region 15; On the surface of the p-well region 1 3 sandwiched between the n + source region 15 and the surface exposed portion 14 (hereinafter referred to as the rT surface region) of the drift layer 12, a gate electrode 18 is provided with an intermediary gate insulating film 17. The n + source region 15 and the surface of the p-well region 13 are in contact with the source electrode 19 in common. In order to reduce the contact resistance with the source electrode 19 on the surface that is in contact with the source electrode 19 of the ρ-well region 13 in the device (Latch up), this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 4 544932 A7 B7 V. Description of the invention (2) To increase the resistance, there may be cases where a P + Contact area 21 is provided. (Please read the precautions on the back before filling in this page.) If the n + drain layer 1 1 which is conductively connected to the drain electrode 20 of the MOSFET in FIG. 36 is changed to a low resistance P + drain layer, it will become a flat type. n-channel vertical IGBT. At this time, from the high-resistance ιΓ drift layer 12 serving as the voltage support layer thereon, the upper structure may be exactly the same as that of the MOSFET of FIG. 36. The operation of the IGBT is controlled by the signal to the gate electrode. The current flowing from the drain electrode to the source electrode is the same, except that the MOSFET is a unipolar type device. The IGBT is a bipolar type. The voltage drop of the device when the current flows (ON state) is reduced. The on-resistance (= voltage drop / current) in the on-state of this vertical M0SFET or IGB can be expressed by the sum of the resistance of the current path inside the element, but especially the on-resistance of high-withstand voltage elements The resistance of the high-resistance ^ drift layer 12 portion becomes dominant. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ----- In order to reduce the loss of MOSFET or IGBT or reduce the resistivity of this drift layer 12, it is effective to reduce the thickness. However, since the n_drift layer 12 becomes empty and becomes a withstand voltage support layer in the OFF state, in order to reduce the resistance 値, increasing the impurity concentration, reducing the resistivity, and reducing the thickness of the drift layer 12 may cause resistance. The pressure drops. On the contrary, since a semiconductor device having a high withstand voltage must increase the thickness of the η_drift layer 12, the on-resistance inevitably increases and the loss becomes large. That is, there is a trade-off relationship between the on-resistance and the withstand voltage. This trade-off relationship is not only M0SFET or IGBT, but even in power semiconductor components such as bipolar transistors and diodes, the known difference is also the same. This paper standard applies Chinese National Standard (CNS) Α4 specification (210 × 297 mm) 544932 A7 B7 V. Description of the invention (3) 〇 (Please read the precautions on the back before filling out this page) And, as is known in the above-mentioned device (Device) p-well area 13—general reason The gate electrode layer 18 is formed by introducing impurities as a mask, and thus its planar shape is approximately the reverse shape of the gate electrode layer 18. Fig. 37 and Fig. 38 are plan views showing examples of patterns of the gate electrode 18 of the conventional device. The example of the window shape of the gate electrode 18 of Fig. 37 is a quadrangle, which is disclosed in Japanese Patent Fair 7- 831 Bulletin 23 and the like. The p-well region 13 is formed by introducing impurities through a window of the gate electrode 18, and thus its planar shape becomes a quadrangle. The η + source region 15 is formed into a quadrangular ring shape by introducing impurities with one end of the gate electrode 18 as the window. Inside the window of the gate electrode 18 in FIG. 37, a p-well region 13 and a contact region 24 of a source electrode provided in contact with the n + source region are displayed. The source electrode contact region 24 is also made into a similar quadrangle. An example in which the window shape of the gate electrode 18 of FIG. 38 is a hexagon is disclosed in, for example, USP 4,593,302 and the like. In this case, the planar shape of the p-well region 13 is hexagonal. The source electrode contact region 24 is also made into a similar hexagon. Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs cooperate with Ti to print. On the other hand, regarding the withstand voltage structure of MOS type semiconductor devices, a guard ring structure or an active area is generally provided around the active area. Field electrode structure or resistive film + field electrode structure. [Explanation of invention] However, the general withstand voltage can only achieve the semiconductor substrate used in any case of withstand voltage structure and the ideal withstand voltage calculated below 90% of the withstand voltage structure. The Chinese paper standard (CNS) A4 Specifications (210X 297 mm) 544932 A7 B7 V. Description of the invention (4). (Please read the precautions on the back before filling in this page.) Therefore, to achieve the target withstand voltage, it is necessary to increase the thickness of the semiconductor substrate or use a withstand voltage structure with a margin, even in devices that require low on-resistance. (Device) cannot increase the on resistance. One of the reasons that only about 90% of the withstand pressure calculated by the structure can be realized is that there is a problem with the plane arrangement method of the active part, and the other is that the withstand voltage structure part is not optimized, It also breaks down in the pressure-resistant structure. Each will be described in detail below. First, regarding the active region, the shape of the P-well region 13 is as shown in FIGS. 37 and 38, and each of the P-well regions 13 becomes a shape surrounded by the n_drift surface portion 14 of the drift layer 12. In other words, since the n_drift surface portion 14 and the p-well region 13 are convex, the electric field intensity of the pn junction portion therebetween becomes higher due to the shape effect, and becomes higher than the impurity concentration of the drift layer 12 and the p-well region 13 originally. The determined withstand voltage is also low. Accordingly, in order to ensure the withstand voltage, it is necessary to reduce the impurity concentration of the ΓΓ drift layer 12, and this is a reason for further increasing the on-resistance. A method for suppressing the reduction in withstand voltage caused by the shape effect of the ρ well region 13 is printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, in USP 5,723,890, the main part of the gate electrode is regarded as extending in one direction. Strip method. FIG. 39 is a plan view showing a pattern of the gate electrode 18 thereof. In this case, the planar shape of the main part of the p-well region 13 also becomes a strip. The contact area 24 is also made in a strip shape. However, the MOSFET having the gate electrode 18 in a stripe shape is not without problems. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (5) (Please read the precautions on the back before filling this page) Known quadrangular or hexagonal In the case of a gate electrode of a window, since the control signal is supplied to the gate electrode, the shape of the gate electrode acts on the network, so its gate resistance is suppressed to a low level. However, in the case where the gate electrode 18 is bar-shaped, the control signal supplied to the gate electrode has only a directional path from both ends of the strip, so that an increase in the gate resistance causes an increase in the switching loss described later. The reduction of the MOSFET loss requires a reduction in the on-state loss caused by the on-resistance previously described, and a reduction in the loss during switching. Generally, it is important to reduce the loss during switching, to shorten the switching time, especially to shorten the switching time when the element changes from the on state to the off state. In order to shorten the switching time of the vertical MOSFET, it is necessary to reduce the capacitance Crss formed between the surface region 14 in FIG. 36 and the gate electrode 18 opposed to the intervening gate insulating film 17. Furthermore, it is effective to reduce the width of the? -Surface region 14 sandwiched between the? -Well region 13. However, if the width of the ιΓ surface region 14 sandwiched between the ρ well region 13 is reduced, a resistance component (hereinafter referred to as a JFET resistance) caused by the action of a junction field effect transistor, which is one of the on-resistances of the MOSFET, becomes larger. Connected to the resistance of the Intellectual Property Bureau of the Ministry of Economic Affairs, employee consumer cooperatives printed high. One solution to this problem of increasing the JFET resistance is, for example, the counter dope method disclosed in USP 4,593,302. It is true that the use of this technique can suppress the increase in on-resistance, but even if the JFET resistance is reduced slightly, increasing the width of the 11_surface region 14 will be related to the drop in withstand voltage. In order to avoid this drop in withstand voltage, it is necessary to reduce the amount of reverse doping. As a result, there is a problem of falling into a circle that reduces the effect of suppressing the increase in the resistance of the JFET. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (6) (Please read the precautions on the back before filling this page) And in order to reduce the switching loss, in addition to the above Crss The reduction in the amount of external gate drive charge Q g is also effective. Q g is calculated by charging the charge capacitance Ciss of the MOS device from 0 (V) to the drive voltage V1 (V) with the voltage Vgs between the source and the source, and is expressed by the following formula. [Number 1]
Qg= S 〇vlCiss · VgsdC/dV 由上式得知降低Ciss係與Qg的降低有關。 在MOS型裝置的Ciss係端子間電容，以下式表示。Qg = S ovlCiss · VgsdC / dV It is known from the above formula that the decrease in Ciss is related to the decrease in Qg. The capacitance between Ciss terminals of a MOS device is expressed by the following formula.
Ciss = Cgs + Cgd 此處，Cgs爲閘極/源極間電容，Cgd爲閘極/汲極間電 容（ = Crss) 0 對於Crss的降低，除了先前所記載的利用藉由反摻雜 的JFET電阻的降低之解決策外，也有其他的解決策。圖40 係採取其他解決策的MOSFET的剖面圖。在面對n_表面區 域14的閘極絕緣膜17的一部分配設厚的閘極絕緣膜25，謀 求C r s s的降低。 經濟部智慧財產局員工消費合作社印製 但是這種情形因在閘極絕緣膜17與厚的閘極絕緣膜25 的絕緣膜產生層差，故有引起層差部分的電場強度升高、 耐壓下降的問題。 再者對於Cgs的降低，可考慮縮小閘電極18的面積之 方法，惟例如圖39所示的條狀閘電極的情形，若使閘電極 的寬度變細的話，前述的裝置內部的閘電阻增加、開關損 失增加。 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） 544932 A7 B7 五、發明説明（7 ) (請先閱讀背面之注意事項再填寫本頁) 另一方面關於耐壓構造部，在與配置於電壓支持層的 n_漂移層12上的源電極19等電位的p井區域13的最外周部中 ，P井區域13與ιΓ漂移層12之間的pn接合（Junction)因具有 曲率，故在電壓施加時此曲率部分的電場強度比平面接合 的情形還增大，在比由耐壓支持層的構造計算的耐壓還低 的施加電壓到達臨界電場強度而崩潰（Breakdown)。 鑒於如以上的種種問題，本發明的目的爲提供大幅地 改善接通電阻與耐壓的取捨（Trade-off)關係，謀求高耐壓同 時降低接通電阻，再者，開關損失的降低也能同時實現的 半導體元件。 爲了上述課題的解決本發明係一種半導體裝置，其特 徵包含： 第一或第二導電型的低電阻層； 電壓支持層，包含配置於其低電阻層上的至少第一導 電形半導體區域； 第二導電型井區域，配置於電壓支持層的表面層； 經濟部智慧財產局員工消費合作社印製 第一導電型源極區域，配置於其第二導電型井區域的 表面層； 閘電極，在被夾於電壓支持層被第二導電型井區域包 圍到達表面的部分之第一導電型表面區域與第一導電型源 極區域的第二導電型井區域的表面上，中介閘極絕緣膜而 配設； 源電極，在第一導電型源極區域與第二導電型井區域 的表面共通地接觸而配設；以及 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） +Θ---- 544932 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（8 ) 汲電極，配設於該低電阻層的背面側，其中採取以下 的手段。 首先，令電壓支持層到達表面的部分之第一導電型表 面區域被第二導電型井區域包圍。 據此，與第二導電型井區域被第一導電形表面區域包 圍而配置的構造之習知的裝置不同，可抑制因第二導電形 井區域的形狀效應所造成的電場強度的增加，即使使電壓 支持層低電阻化，也能確保高耐壓。而且，若使電壓支持 層低電阻化的話，可實現低接通電阻。 再者，藉由減小被前述第二導電形井包圍而配置的第 一導電形表面區域對包含具備前述半導體表面中的MOS構 造的第一導電形源極區域之第二導電形井區域的表面積的 面積比率，可降低第一導電形表面區域與中介閘極絕緣膜 而對向的閘電極之間所構成的電容Crss。但是，若減小前 述半導體表面的第一導電型表面區域的面積比率的話，如 先前所說明的接通電阻升高。 關於改變此第一導電形表面區域的面積比率之試作裝 置的其面積比率與先前記載的閘極/汲極間電容Crs s以及接 通電阻Ron的關係如圖6所示。橫軸係第一導電形表面區域 對包含第一導電形源極區域的第二導電形井區域的表面積 的面積比率，縱軸係Crss以及Ron。此外，此試作實驗係 以令後述的實施例一的型式的主動區域（Active area)的面積 爲約16mm2的η通道MOSFET來進行。第一導電形表面區域 的長度爲3.6mm。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 544932 A7 B7 五、發明説明（9 ) 由圖6得知Crss與第一導電形表面區域的面積比率成比 例而變大。因此，面積比率儘可能小者較佳’對於令Crss (請先閲讀背面之注意事項再填寫本頁) 爲在實裝置可容許的15pF以下，需令面積比率爲〇·23以下 〇 另一方面Ron在第一導電形表面區域的面積比率爲0.1 5 到0.2爲最小。若面積比率比0.2還大的話’緩緩地增大，惟 相反地若比0.01還小，則急速地增大。因此’爲了抑制Ron 到實裝置可容許的最小値的兩倍以下，需令面積比率爲0.01 以上。 綜合上述’最好令面積比率爲0.01〜的$b圍。據此’ 可實現兼備低接通電阻與低Crss的裝置。 其次，表面中的第一導電型表面區域的形狀係對寬度 形成長度長的條狀。 經濟部智慧財產局員工消費合作社印製 如此因條狀的第一導電型表面區域還被第二導電型井 區域包圍，故與如習知的裝置的第二導電型井區域被第一 導電型表面區域包圍而配置的構造不同，可抑制因第二導 電型井區域的形狀效應所造成的電場強度的增加，即使使 電壓支持層低電阻化也能確保高的耐壓。 再者，令前述半導體表面中的前述條狀的第一導電型 表面區域的主要部分的寬度爲0.1〜2// m的範圍。 藉由減小第一導電型表面區域的條寬，可降低第一導 電形表面區域與中介閘極絕緣膜而對向的閘電極之間所構 成的電容Crss。但是，同時接通電阻升高。 關於改變第一導電形表面區域的寬度之試作裝置 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4^ 544932 A7 B7 五、發明説明（10 ) (請先閲讀背面之注意事項再填寫本頁) (Device)的第一導電形表面區域的寬度與Crss以及接通電阻 Ron的關係如圖7所示。橫軸係第一導電形表面區域的寬度 ，縱軸係Crss以及Ron。令第一導電形表面區域的長度爲 3·6mm 〇 由圖7得知Crss與第一導電形表面區域的寬度成比例而 變大。因此，寬度儘可能小者較佳，對於令Crss爲在實裝 置可容許的15pF以下，需令寬度爲約3// m以下。 另一方面Ron在第一導電形表面區域的寬度爲1.5到2 // m爲最小。若寬度比2.5 // m還大則緩緩地增大，惟相反 地若比0.1 // m還小則急速地增大。因此，爲了抑制Ron到 實裝置可容許的最小値的兩倍以下，需令寬度爲0. 1 // m以 上。 如此，在汲極區域爲短範圍接通電阻與Crss有取捨的 關係。實際使用上對於以低接通電阻使低Crss兩立，因最 好Crss爲15pF以下、接通電阻爲1.5Ω以下，故第一導電型 表面區域的寬度被限定於0. 1 // m以上、2 // m以下的範圍 。如此若能實現小的Crss的話，可減小開關損失。 經濟部智慧財產局員工消費合作社印製 而且，若條狀的第一導電型表面區域的主要部分的寬 度擴大的話，在表面的電場強度升高、耐壓降低。另一方 面，若上述表面汲極區域的主要部分寬度變窄的話，JFET 電阻增加、接通電阻升高，惟如上述藉由限定最佳的尺寸 範圍，使耐壓不降低接通電阻不升高的裝置爲可能。 即使在條狀的第一導電型表面區域的情形，藉由減小 被前述第二導電形井區域包圍而配置的第一導電形表面區 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（11 ) (請先閱讀背面之注意事項再填寫本頁) 域對第二導電形井區域與第一導電形源極區域的表面積和 之面積比率，可降低第一導電形表面區域與中介閘極絕緣 膜而對向的閘電極之間所構成的電容Ci*ss。同時接通電阻 增大，惟如先前所述的，藉由限定第一導電型表面區域的 面積比率的範圍，使不引起耐壓的降低，在接通電阻增加 的容許範圍內也能抑制Crss於很小的裝置（Device)爲可能。 藉由以在一個裝置（Device)內滿足幾個手段的構造，使 性能更提高的裝置爲可能。 若條狀的第一導電型表面區域的長度變長的話，因在 同一面積的通道寬度擴大，故接通電阻降低，惟另一方面 裝置（Device)內部的閘電阻升高，如此開關時間變慢、開關 損失增加。 相反地，在第一導電型表面區域的長度方向的途中配 設聞電極等，若縮短長度的話，因藉由減小裝置（Device)內 部的閘電阻、縮短開關時間，使降低開關損失的在同一面 積的通道寬度變窄，故接通電阻升高。 即限定第一導電型表面區域的長度於適當的範圍很重 經濟部智慧財產局員工消費合作社印製 要。 關於改變第一導電形表面區域的長度之試作裝置 (Device)的支配第一導電形表面區域的長度與開關時間的輸 入電容Crss以及接通電阻Ron的關係如圖8、9、10、11所 示。橫軸係第一導電形表面區域長度，縱軸係Crss或R0n 。令第一導電形表面區域的寬度爲1.6//m、表面積比率爲 0.12。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X；297公釐） ------ 544932 A7 _ B7 五、發明説明（12) (請先閱讀背面之注意事項再填寫本頁) 在圖8中若第一導電形表面區域的長度爲500 // m以上的 話’ Crss變成幾乎不變的値，惟在500 // m以下則顯示慢慢 地增加。 圖9係圖8之中的第一導電形表面區域的長度擴大400 # m以下的部分之特性圖。由此得知爲了縮短開關時間， 沿著η·表面區域的一方向的長度爲100// m以上，較佳應限 疋爲500/zm以上。 其次，與接通電阻的關係顯示於圖10與圖11。如圖10 可見到的，若第一導電形表面區域的長度爲500 // m以上的 話，接通電阻變成幾乎不變的値，惟在500 // m以下則顯示 慢慢地增加。圖11係擴大圖10之中的汲極區域的長度爲400 // m以下的部分之特性。由圖1 1若接通電阻爲1 〇〇 // m以下 的話急遽地增大。由此得知爲了降低接通電阻，沿著ιΓ表 面區域的一方向的長度爲100// m以上，特別是應限定於500 # m以上。 如此，可實現低接通電阻、開關損失小的裝置（Device) 〇 經濟部智慧財產局員工消費合作社印製 而且，閘電極爲條狀的複數個部分也可以。 若以這種閘電極爲罩幕（Mask)形成第二導電形井區域的 話，在其下方必然地形成有被第二導電形井區域包圍周圍 的條狀之第一導電型表面區域。 先前記載第一導電型表面區域的寬度限定於〇· 1 # m以 上、2//m以下的範圍。第一導電型表面區域的寬度係由成 爲形成第二導電形井區域時的罩幕之閘電極的寬度與對雜 _ —_- -_—____ 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（13) (請先閱讀背面之注意事項再填寫本頁) 質濃度的橫方向的擴散距離來決定。因此，爲了使第一導 電型表面區域的寬度在上述的適當値，若令橫方向擴散距 離爲不足約2 // m的話，令聞電極的寬度爲4〜8 // m、最最好 爲5〜7 // m較佳。 而且，因以相同理由第一導電型表面區域的長度係藉 由條狀閘電極的長度來決定，故關於條狀閘電極的値也令 其爲先前所記載的第一導電型表面區域的適當値之l〇〇//m 以上、最好爲500 // m以上較佳。 若爲具有連接條狀的閘電極間的寬度窄的橋接（Bridge) 部分，可降低閘電阻。 而且，令該閘電極的橋接部分寬度爲4 // m未滿。若未 滿4 // m的話，令形成第二導電形井區域時的橫方向擴散距 離爲約2 // m，則橋接部分的下方藉由來自兩側的擴散而連 接第二導電形井區域，形成包圍第一導電型表面區域的第 二導電型井區域。 關於閘電極的橋接部分的配置頻率，每一閘電極的長 度50// m —個以下，較佳爲以每25 0 // m —個以下。 經濟部智慧財產局員工消費合作社印製 若配設多數閘電極的橋接部分的話，因裝置（Device)內 部的閘電阻小的閘極/汲極間電容Cgd增加，故開關速度變 慢、開關損失增加。而且，閘電極的下方藉由來自兩側的 擴散而連接第二導電形井區域，惟因形成於其表面層的第 一導電型源極區域的擴散深度淺，故橫方向擴散距離也不 會短短地連接。因此，閘電極的橋接部分下方不形成通道 變成無效區域，在同一面積的通道寬度變窄，故接通電阻 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） 544932 Α7 Β7 五、發明説明（14 ) 升高。橋接部分隨便地增加數目並非上策。條狀閘電極的 長度100 μ m、最好在500 # m之間不配設一個以上較佳。 (請先閲讀背面之注意事項再填寫本頁) 前述電壓支持層即使由第一導電型的半導體區域所構 成，接近第一導電型的半導體區域表面的部分爲高電阻層 、下側即使由低電阻層所構成’而且以交互地配置第一導 電型半導體區域與第二導電型半導體區域的所謂超接合型 也可以。 其次，關於用以提高耐壓的耐壓構造部分採取如以下 的手段。 首先，一種半導體裝置，包含： 第一或第二導電型的低電阻層； 電壓支持層，包含配置於其低電阻層上的至少第一導 電形半導體區域； 第二導電型井區域，配置於電壓支持層的表面層；以 及 複數個第二導電型護環，在半導體表面中包圍該第二 導電型井區域而配置，其中 經濟部智慧財產局員工消費合作社印製 當令半導體裝置的耐壓爲Vbr(V)、該複數個第二導電 型護環的數目爲η(條）時，令η爲1.〇xVbr/100以上，更佳爲 1.5xVbr/100以上。 關於改變第二導電型護環的數目η(條）的二次元模擬 (Simulation)與試作裝置（Device)的護環的數目 η與耐應 Vbr(V)的關係顯示於圖14。橫軸爲耐壓Vbr(V)、縱軸爲護 環的數目η。 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210Χ297公釐） 47- 544932 A7 B7 五、發明説明（15 ) (請先閲讀背面之注意事項再填寫本頁) 實驗所使用的n_漂移層的特性，對Si有雜質使用磷的 晶圓的特性之電阻率p =18 Ω cm、厚度t = 48.5 // m的Si(bl線 )，與 p=32.5Qcm、t = 76.5//m 的 Si(b2 線）兩種類。 各晶圓都隨著護環的條數增加使耐壓Vbr也升高。但 是，在由11_漂移層的Si特性計算的平面接合的情形的理論 耐壓（分別爲654V、1011V)的97〜98%左右的耐壓飽和，超過 此即使增加護環條數耐壓也不會變化。 護環的數目η其急速地提高耐壓的區域完了的邊界被 n=l.CUVbi7100的式（b3線）規定。再者，顯示成爲即使增加護 環條數也幾乎不引起耐壓增加的耐壓之護環條數的關係爲 n=1.5xVbr/100(b4線）。 習知技術的耐壓構造因止於由前述Si特性計算的平面 接合耐壓的9 0 %左右，故藉由以上式表示的以上的護環條數 ，可期待高耐壓化的功效。 另一方面，η的上限規定爲6.(UVbr/100以下。 經濟部智慧財產局員工消費合作社印製 若增加護環的條數則耐壓構造寬度變廣’在實際裝置 (Device)產生晶片尺寸變大的弊害。由圖14因即使增加護環 條數耐壓也飽和，故設置護環條數的上限係實際的。此上 限係考慮對以適用本發明的裝置的耐久性試驗等所想定的 耐壓構造表面的電荷儲存效應之耐量’本發明的功效所開 始的關係之護環條數的大約6倍爲相當。即該關係式爲 n = 6. Ox Vbr/1 00。藉由以此關係式以下的護環條數，可防止 裝置表面的電荷儲存效應，同時可實現晶片尺寸小、高耐 壓化。 ___________—-- 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210Χ297公釐） 544932 A7 B7 五、發明説明（16 ) (請先閲讀背面之注意事項再填寫本頁) 其次，令第二導電型井區域與自第二導電型井區域側 數起第一個第二導電型護環之間隔爲1 // m以下，較佳爲0.5 # m以下。 關於改變第二導電型井區域與第一個第二導電型護環 之間隔的二次元模擬與試作裝置所求出的間隔與耐壓 Vbr(V)的關係顯示於圖15。橫軸爲間隔（// m)，縱軸爲耐壓 Vbr(V)。此時的n_漂移層的特性係使用p =22.5 Ω cm、厚度 t = 57.0//m的Si。p井區域、護環的接合深度爲3.5//m。 隨著自P井區域到護環爲止的間隔分離，耐壓單調地 下降，在3 // m η·漂移層與習知耐壓構造的組合的耐壓（C2線 )大致相同。 由圖1 5得知藉由令p井區域與第一條護環的間隔爲1 // m以下，可確保ιΓ漂移層所具有的耐壓的大約95%以上 (c 1線），比習知構造（c 2線）還能提高5 %的耐壓。再者，若令 ρ井區域與第一條護環的間隔爲〇. 5 // m以下，耐壓比習知 構造還提尚約7.5%。 經濟部智慧財產局員工消費合作社印製 接通電阻與耐壓的關係已知爲Ron 〇〇Vbr2·5。因此，若 令間隔爲0.5 // m以下的話，可降低接通電阻的20%，可獲得 劃期的效應。 除此之外，前述井與前述第一個護環在半導體表面部 分連接的情形，若表面部的連接部分空乏化的話，電場強 度的緩和效應最大耐壓可最高。 此外在圖1 5，由顯示P井區域與第一條護環的連接之0 //m到顯示p井與護環的重疊之負的尺寸區域爲止耐壓上 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（17 ) (請先閲讀背面之注意事項再填寫本頁) 升，在-1 // m左右飽和。此理由乃係若護環自p井區域分離 的話，因p井區域的pn接合的曲率形狀造成電場強度增加 發生耐壓降低，若接近的話對曲率形狀的電場強度被緩和 ’ P井區域與護環的重疊在1 # m左右曲率形狀效應大致消 失。 再者，令自第二導電型井區域側數起第一個與第二個 第二導電型護環之間隔爲1.5 // m以下、較佳爲1. 〇 # m以下 、更佳爲0.5 // m以下。 關於改變第一個與第二個第二導電型護環之間隔的二 次元模擬與試作裝置所求出的間隔與耐壓Vbr(V)的關係顯 示於圖16。橫軸爲間隔（// m)，縱軸爲耐壓vbi*(V)。 P井區域與第一條護環的間隔爲〇. 5 // m係以d 1線表示 ’爲1 · 0 // m係以d 2線表示，爲1 · 5 // m係以d 3線表示。在第 二條以後的護環所求出的重要項目爲如何不降低在第一條 護環設定的耐壓。因此，藉由令第一條與第二條護環之間 隔爲1.5/z m以下，可確保以p井與第一條護環的關係決定 的耐壓之大約98%以上。藉由以1·0// m以下、0.5 // m以下 經濟部智慧財產局員工消費合作社印製 使可分別確保99%以上、大約99.5 %以上的耐壓構造爲可能 〇 與以上所述的理由相同，越縮小第一個護環與第二個 護環的間隔，與電壓支持層的接合部分的電場強度越能緩 和，使高耐壓化爲可能。 再者，令自第二導電型井區域側數起第二個與第三個 第二導電型護環之間隔爲2.0// m以下、較佳爲1.0// m以下 本紙張尺度適用中國國家標赛（CNS ) Α4規格（210Χ297公釐） - 544932 Α7 _____ Β7 五、發明説明（18 ) 〇 (請先閱讀背面之注意事項再填寫本頁) 關於改變第二個與第三個第二導電型護環之間隔的二 次元模擬與試作裝置所求出的間隔與耐壓vbr(v)m關係顯 不方^表1。參數爲弟一^導電型井區域與第一^個第二導電刑ig 環之間隔。令第一個與第二個第二導電型護環之間隔爲i .〇 // m 〇 [表1] " --------- 三條護環的間隔與耐厭 P井區域與 第一條與 第二條與 耐 壓 對li與I2的 第一條的 第二條的 第三條的 Vbr( V) 組合之比 間隔 間隔 間隔 率（％) li ( // m) h( β m) h{ μ m) 0.5 1.0 1.0 738 99.6 0.5 1.0 2.0 737 99.4 1.0 1.0 1.0 732 99.6 1.0 1.0 2.0 730 99.3 經濟部智慧財產局員工消費合作社印製 任何一個都藉由令第二條與第Η條護環的間隔爲2.0 // m以下’可確保ρ井與第一條、以第一條與第二條護環 決定的耐壓的大約99%以上。若令1.〇 e m以下，則可確保前 述耐壓的大約9 9 · 5 %以上。這些與前述相同，可緩和接合部 分的電場強度，使高耐壓化爲可能。 若令第三個第二導電型護環與第四個第二導電型護環 i紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐f--— 544932 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（19 ) 之間隔爲2.5// m以下，較佳爲2.0// m以下，同樣地可緩和 接合部分的電場強度，使高耐壓化爲可能。 當令第二導電型并區域與第二導電型護環之中的接合 深度淺的深度爲心時，令前述第二導電型井區域與自第二 導電型井區域側數起第一個第二導電型護環之間隔爲d!/4 以下，較佳爲ch/8以下。 這些稍微改變看法，以第二導電型井區域或第二導電 型護環的接合深度爲基準，規定第二導電型井區域與第一 個第二導電型護環之間隔。與前述一樣可緩和接合部分的 電場強度，使高耐壓化爲可能。 而且，令第二導電型護環的接合深度爲d2時，令第一 個第二導電型護環與第二個第二導電型護環之間隔爲d2/4 以下，較佳爲d2/8以下。 再者，令第二個第二導電型護環與第三個第二導電型 護環之間隔爲d2/4以下，較佳爲d2/8以下。 這些也改變看法，以第二導電型護環的接合深度爲基 準，規定第一個第二導電型護環與第二個第二導電型護環 ，或第二個第二導電型護環與第三個第二導電型護環之間 隔。與前述一樣可緩和接合部分的電場強度，使高耐壓化 爲可能。 當令第二導電型井區域與第一個第二導電型護環之間 隔爲h，第一個第二導電型護環與第二個第二導電型護環 之間隔爲12時，令l2-h爲l//m以下，當令第一個第二導電 型護環與第二個第二導電型護環之間隔爲h，第二個第二 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 22 544932 A7 B7 五、發明説明（20 ) (請先閲讀背面之注意事項再填寫本頁) 導電型護環與第三個第二導電型護環之間隔爲13時，令13-12 爲l//m以下。再者，當令第二個第二導電型護環與第三個 第二導電型護環之間隔爲h，第三個第二導電型護環與第 四個第二導電型護環之間隔爲14時，令：U-h爲1 // m以下。 這點也改變看法，若相鄰的兩個間隔過於不同的話， 在大的部分電場強度升高而降伏。爲了避免此現象，至少 到第四個護環附近，令相鄰的兩個間隔的差爲1 // m以下。 但是，若設定間隔的差1 2 - 1 1、1 3 - 1 2、1 4 - 1 3爲比〇 · 5 // m還 小的話，雖然有降低耐壓的效果，惟因護環間的電位差變 小尺寸效率變差，故最好至少0.2// m以上，間隔的差爲〇.5 // m左右，即0.2〜0.8// m的範圍爲最佳。 對於第二導電型護環的數目多的情形，關於其寬度規 定例如第一個第二導電型護環的寬度比第五個第二導電型 護環的寬度大，第二個第二導電型護環的寬度比第六個第 二導電型護環的寬度大，第三個第二導電型護環的寬度比 第七個第二導電型護環的寬度大。 經濟部智慧財產局員工消費合作社印製 據此，可緩和成爲比外側的護環附近還高的電場強度 之內側的護環的電場強度。 再者，在第二導電型井區域與第一個第二導電型護環 之間的前述電壓支持層表面，中介絕緣膜配置導電體膜。 如此藉由配置導電體膜因可遮蔽耐壓構造表面的電荷 帶給半導體表面的影響，故可確保穩定的耐壓。 特別是令前述導電體膜爲浮置（Floating)電位。 上述的效果即使前述導電體爲浮置電位效果也不變， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（21 ) 故無須與接鄰的同樣的導電體膜連接。 (請先閱讀背面之注意事項再填寫本頁) 完全一樣地，在第一個第二導電型護環與第二個第二 導電型護環之間、第二個第二導電型護環與第三個第二導 電型護環之間、第三個第二導電型護環與第四個第二導電 型護環之間的前述電壓支持層表面，中介絕緣膜配置導電 體膜也能獲得相同的效果。 而且，令這些導電體膜爲浮置電位也可以。 前述電壓支持層由第一導電型的半導體區域所構成， 第一導電型的半導體區域的表面側爲高電阻層，下側由低 電阻層所構成，而且，以交互地配置第一導電型半導體區 域與第二導電型半導體區域之所謂超接合型也可以。 在半導體裝置的表面爲了保護，配置由有機高分子材 料膜所構成的保護膜。 經濟部智慧財產局員工消費合作社印製 若被配置於半導體表面的第二導電型井區域包圍而配 置的第一導電型表面區域的比前述第二導電型井區域還淺 的區域中的電阻率，係較比前述第二導電型井區域還深的 區域的電壓支持層的電阻率還低較佳，令第一導電型表面 區域的磷離子的摻雜量爲2xl〇12〜5xl〇12cm_2，較佳爲 2·5χ1012〜4.0xl012cm-2。 據此，與先前所述的反摻雜法相同，對被第二導電型 井區域包圍而配置的表面汲極區域中的JFET電阻的降低有 效果。特別是在本發明’因規定表面汲極區域的面積比率 比習知的還小，故；IFET電阻常變大，反摻雜的效果也大。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 544932 A7 B7 五、發明説明（22 ) 【圖式之簡單說明】 圖1係本發明實施例一之η通道縱型MOSFET的基板表 (請先閱讀背面之注意事項再填寫本頁) 面之俯視圖。 圖2係實施例一之η通道縱型MOSFET的主動部分之部 分剖面圖。 圖3係實施例一之η通道縱型MOSFET晶片的金屬電極 俯視圖。 圖4係實施例一之η通道縱型MOSFET的閘電極、源電 極配置圖。 圖5係沿著圖1的A-A線的部分剖面圖。 圖6係顯示試作的η通道縱型MOSFET中的表面η汲極 區域面積比率與Crss、Ron的關係之特性圖。 圖7係顯示試作的η通道縱型MOSFET中的表面η汲極 區域的主要部分的寬度與Crss、Ron的關係之特性圖。 圖8係顯示試作的η通道縱型MOSFET中的表面η汲極 區域的長度與Ciss的關係之特性圖。 經濟部智慧財產局員工消費合作社印製 圖9係顯示試作的η通道縱型MOSFET中的表面η汲極 區域的長度與Ciss的關係之特性圖。 圖10係顯示試作的η通道縱型MOSFET中的表面η汲 極區域的長度與Ron的關係之特性圖。 圖11係顯示試作的η通道縱型MOSFET中的表面η汲 極區域的長度與Ron的關係之特性圖。 圖12係比較本發明的n通道縱型MOSFET以及比較例 中的耐壓與RonA的關係之比較圖。Ciss = Cgs + Cgd Here, Cgs is the gate-to-source capacitance and Cgd is the gate-to-drain capacitance (= Crss) 0 For the reduction of Crss, except for the previously described use of JFET with anti-doping There are other solution decisions besides the reduction of resistance. Figure 40 is a cross-sectional view of a MOSFET with other solutions. A portion of the gate insulating film 17 facing the n_surface region 14 is provided with a thick gate insulating film 25 to reduce C r s s. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, in this case, a layer difference occurs in the insulating film of the gate insulating film 17 and the thick gate insulating film 25, which causes an increase in the electric field strength and voltage resistance of the stepped portion. The problem of falling. Furthermore, for the reduction of Cgs, a method of reducing the area of the gate electrode 18 can be considered. However, for example, in the case of a stripe gate electrode as shown in FIG. 39, if the width of the gate electrode is made thinner, the gate resistance inside the aforementioned device increases. , Switching losses increase. This paper size applies Chinese National Standard (CNS) A4 specification (210x297 mm) 544932 A7 B7 V. Description of invention (7) (Please read the precautions on the back before filling this page) On the other hand, the pressure structure department, In the outermost peripheral portion of the p-well region 13 which is equipotential to the source electrode 19 disposed on the n_drift layer 12 of the voltage support layer, the pn junction between the P-well region 13 and the ιΓ drift layer 12 has curvature. Therefore, when the voltage is applied, the electric field strength of this curvature portion is larger than that in the case of planar bonding, and the applied voltage lower than the withstand voltage calculated from the structure of the withstand voltage support layer reaches the critical electric field strength and breaks down (Breakdown). In view of the above problems, an object of the present invention is to provide a significantly improved trade-off relationship between the on-resistance and the withstand voltage, so as to achieve a high withstand voltage while reducing the on-resistance. Furthermore, the reduction of switching loss can also be achieved. Simultaneous implementation of semiconductor elements. In order to solve the above problems, the present invention is a semiconductor device including: a low-resistance layer of a first or second conductivity type; a voltage support layer including at least a first conductive semiconductor region disposed on the low-resistance layer; The area of two conductive wells is arranged on the surface layer of the voltage support layer; the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the first conductive source area and arranged on the surface layer of its second conductive well area; The surface of the first conductive type surface region of the voltage support layer surrounded by the second conductive type well region and reaching the surface and the surface of the second conductive type well region of the first conductive source region are mediated by a gate insulating film. Configuration; The source electrode is arranged on the surface of the first conductivity type source region and the surface of the second conductivity type well in common contact; and this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) + Θ ---- 544932 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (8) The drain electrode is arranged on the back side of the low-resistance layer, where Take the following means. First, the first conductive type surface area of the portion where the voltage support layer reaches the surface is surrounded by the second conductive type well area. According to this, unlike the conventional device having a structure in which the second conductive type well region is surrounded by the first conductive type surface region, it is possible to suppress an increase in electric field strength due to the shape effect of the second conductive type well region, even if Reducing the resistance of the voltage support layer also ensures high withstand voltage. Furthermore, if the voltage supporting layer is made low in resistance, a low on-resistance can be realized. In addition, by reducing the area of the first conductive surface area disposed by being surrounded by the second conductive well, the area of the second conductive well including the first conductive source area having the MOS structure in the semiconductor surface is reduced. The area ratio of the surface area can reduce the capacitance Crss formed between the first conductive surface area and the gate electrode facing the intervening gate insulating film. However, if the area ratio of the first-conductivity-type surface area of the semiconductor surface is decreased, the on-resistance increases as described above. The relationship between the area ratio and the gate / drain capacitance Crs s and the on-resistance Ron described in the trial device for changing the area ratio of the first conductive surface area is shown in FIG. 6. The horizontal axis is the area ratio of the first conductive surface area to the surface area of the second conductive well region including the first conductive source region, and the vertical axis is Crss and Ron. In addition, this trial operation was performed with an n-channel MOSFET having an active area of about 16 mm2 in the type of the first embodiment described later. The length of the first conductive surface area is 3.6 mm. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the notes on the back before filling this page) 544932 A7 B7 V. Description of the invention (9) Figure 6 shows that Crss and the first The area ratio of the conductive-type surface area becomes larger in proportion. Therefore, it is better to have the area ratio as small as possible. To make Crss (please read the precautions on the back before filling out this page) is 15 pF or less allowed by the actual device, it is necessary to make the area ratio 0.02 or less. The area ratio of Ron in the first conductive surface area is 0.1 5 to 0.2 as a minimum. If the area ratio is larger than 0.2, it increases gradually, but if it is smaller than 0.01, it increases sharply. Therefore, in order to suppress Ron to less than twice the minimum allowable threshold of the actual device, the area ratio needs to be 0.01 or more. Based on the above, it is preferable to make the area ratio of $ b. Accordingly, a device having both low on-resistance and low Crss can be realized. Next, the shape of the first conductive type surface area in the surface is formed into a stripe shape having a long length with respect to the width. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed such that the strip-shaped surface area of the first conductivity type is also surrounded by the area of the second conductivity type, so the area of the second conductivity type well with the conventional device is the first conductivity type. The structure arranged around the surface area is different, and it is possible to suppress an increase in the electric field strength due to the shape effect of the second conductive type well area, and to ensure a high withstand voltage even if the voltage support layer is made low in resistance. Furthermore, the width of the main portion of the strip-shaped first conductive type surface region in the semiconductor surface is set to a range of 0.1 to 2 // m. By reducing the stripe width of the first conductive surface area, the capacitance Crss formed between the first conductive surface area and the gate electrode facing the intervening gate insulating film can be reduced. However, the on-resistance increases at the same time. Trial device for changing the width of the first conductive surface area The paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) 4 ^ 544932 A7 B7 V. Description of the invention (10) (Please read the notes on the back first (Refill this page) (Device) The relationship between the width of the first conductive surface area, Crss, and on-resistance Ron is shown in Figure 7. The horizontal axis is the width of the first conductive surface area, and the vertical axis is Crss and Ron. Let the length of the first conductive surface area be 3.6 mm. As shown in FIG. 7, Crss becomes larger in proportion to the width of the first conductive surface area. Therefore, it is better to make the width as small as possible. For Crss to be 15 pF or less allowable by the actual device, the width needs to be about 3 // m or less. On the other hand, Ron has a minimum width of 1.5 to 2 // m in the first conductive surface area. If the width is larger than 2.5 // m, it gradually increases, but on the contrary, if it is smaller than 0.1 // m, it increases rapidly. Therefore, in order to suppress Ron to less than twice the minimum allowable threshold of the actual device, the width needs to be 0.1 1 m or more. In this way, there is a trade-off relationship between the on-resistance for the short range in the drain region and Crss. In practical use, for low Crss with low on-resistance, because the best Crss is 15pF or less, and the on-resistance is 1.5Ω or less, the width of the first conductive surface area is limited to 0. 1 // m or more , 2 // range below m. If small Crss can be achieved in this way, switching losses can be reduced. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. If the width of the main portion of the strip-shaped first conductive surface area is increased, the electric field strength on the surface increases and the withstand voltage decreases. On the other hand, if the width of the main part of the surface drain region is narrowed, the JFET resistance increases and the on-resistance increases. However, by limiting the optimal size range, the on-resistance does not decrease and the on-resistance does not increase. Tall installations are possible. Even in the case of the strip-shaped first-conductivity-type surface area, the first-conductivity-type surface area configured by being surrounded by the aforementioned second-conductivity-type well area is reduced in size. This paper applies the Chinese National Standard (CNS) A4 specification (210X297). (Mm) 544932 A7 B7 V. Description of the invention (11) (Please read the notes on the back before filling this page) The ratio of the surface area of the second conductive well area to the first conductive source area is The capacitance Ci * ss formed between the first conductive surface area and the gate electrode facing through the gate insulating film is reduced. At the same time, the on-resistance is increased, but as previously described, by limiting the range of the area ratio of the first conductive surface area, no reduction in withstand voltage is caused, and Crss can be suppressed within the allowable range of on-resistance increase. This is possible with very small devices. With a structure that satisfies several measures in one device, a device with improved performance is possible. If the length of the strip-shaped first-conductivity surface area becomes longer, the channel resistance in the same area increases, so the on-resistance decreases, but on the other hand, the gate resistance inside the device increases, so the switching time becomes longer. Slow, increase switching losses. On the contrary, if the sensation electrode or the like is arranged in the middle of the lengthwise direction of the first conductive type surface area, if the length is shortened, the gate resistance inside the device is reduced and the switching time is shortened. The channel width of the same area becomes narrower, so the on-resistance increases. That is, it is important to limit the length of the surface area of the first conductive type to an appropriate range. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The relationship between the length of the first conductive surface area and the input capacitance Crss and the on-resistance Ron governing the length of the first conductive surface area is shown in Figures 8, 9, 10, and 11. Show. The horizontal axis is the length of the first conductive surface area, and the vertical axis is Crss or R0n. Let the width of the first conductive surface area be 1.6 // m and the surface area ratio be 0.12. This paper size applies Chinese National Standard (CNS) A4 specification (210X; 297 mm) ------ 544932 A7 _ B7 V. Description of the invention (12) (Please read the precautions on the back before filling this page) If the length of the first conductive surface area is greater than 500 // m in FIG. 8, 'Crss becomes almost constant 値, but the value increases slowly below 500 // m. FIG. 9 is a characteristic diagram of a portion where the length of the first conductive surface area in FIG. 8 is enlarged by 400 # m or less. From this, it was found that in order to shorten the switching time, the length in one direction along the η · surface area is 100 // m or more, and the preferred limit 疋 is 500 / zm or more. Next, the relationship with the on-resistance is shown in FIGS. 10 and 11. As can be seen in Fig. 10, if the length of the first conductive surface area is more than 500 // m, the on-resistance becomes almost constant 値, but below 500 // m shows a slow increase. FIG. 11 is a characteristic in which the length of the drain region in FIG. 10 is 400 / m or less. As shown in Fig. 11, if the on-resistance is below 1000 / m, it will increase sharply. From this, it was found that in order to reduce the on-resistance, the length in one direction along the surface area of ιΓ is 100 // m or more, and in particular, it should be limited to 500 #m or more. In this way, a device with a low on-resistance and small switching loss can be realized. ○ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Moreover, the gate electrode may be a plurality of strip-shaped parts. If such a gate electrode is used as a mask to form the second conductive well region, a strip-shaped first conductive type surface region surrounded by the second conductive well region is necessarily formed below it. It has been described that the width of the first conductive type surface area is limited to a range of 0.1 m or more and 2 // m or less. The width of the surface area of the first conductive type is determined by the width of the gate electrode of the mask when forming the area of the second conductive type and the countermeasures _ —_- -_______ This paper size is applicable to China National Standard (CNS) A4 Specifications (210X297 mm) 544932 A7 B7 V. Description of the invention (13) (Please read the precautions on the back before filling this page) The lateral diffusion distance of the mass concentration is determined. Therefore, in order to make the width of the first conductive type surface region as appropriate as described above, if the lateral diffusion distance is less than about 2 // m, the width of the electrode is 4 to 8 // m, and the most preferable is 5 ~ 7 // m is better. Furthermore, since the length of the first conductivity type surface area is determined by the length of the stripe gate electrode for the same reason, the 値 of the stripe gate electrode also makes it appropriate for the first conductivity type surface area described previously. It is more preferably 100 // m or more, preferably 500 // m or more. In the case of a bridge portion having a narrow width between the strip-shaped gate electrodes, the gate resistance can be reduced. In addition, the width of the bridging portion of the gate electrode is set to 4 // m. If it is less than 4 // m, the lateral diffusion distance when forming the second conductive well region is about 2 // m, and the lower part of the bridge portion is connected to the second conductive well region by diffusion from both sides. To form a second conductivity type well region surrounding the first conductivity type surface area. Regarding the arrangement frequency of the bridging part of the gate electrode, the length of each gate electrode is 50 // m-1 or less, preferably every 25 0 / m--1 or less. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. If the bridge part of most gate electrodes is provided, the gate / drain capacitance Cgd of the device with a small gate resistance increases, so the switching speed is slow and the switching loss increase. In addition, the second conductive well region is connected to the lower part of the gate electrode by diffusion from both sides. However, since the first conductive source region formed on the surface layer has a shallow diffusion depth, the diffusion distance in the horizontal direction is also not large. Connect shortly. Therefore, the channel is not formed under the bridging part of the gate electrode and becomes an invalid area. The channel width in the same area becomes narrower. Therefore, the on-resistance of this paper applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 544932 Α7 Β7 Fifth, the description of the invention (14) increased. It is not a good idea to increase the number of bridging parts casually. The length of the stripe gate electrode is 100 μm, and it is better not to arrange more than one between 500 #m. (Please read the precautions on the back before filling this page.) Even if the voltage support layer is composed of a semiconductor region of the first conductivity type, the part close to the surface of the semiconductor region of the first conductivity type is a high-resistance layer. The resistive layer may be a so-called super-junction type in which the first conductive type semiconductor region and the second conductive type semiconductor region are alternately arranged. Next, regarding the pressure-resistant structure part for improving the pressure resistance, the following measures are taken. First, a semiconductor device includes: a low-resistance layer of a first or second conductivity type; a voltage support layer including at least a first conductivity-type semiconductor region disposed on its low-resistance layer; a second conductivity-type well region disposed on The surface layer of the voltage support layer; and a plurality of second conductive type guard rings, which are arranged on the surface of the semiconductor to surround the second conductive type well area. Among them, the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the semiconductor device withstand voltage as When Vbr (V) and the number of the plurality of second conductive type guard rings are η (bars), let η be 1.0 × Vbr / 100 or more, and more preferably 1.5xVbr / 100 or more. The relationship between the two-dimensional simulation (Simulation) of changing the number η (strips) of the second conductive type guard rings and the number of guard rings of the trial device (Device) and the resistance Vbr (V) is shown in FIG. 14. The horizontal axis is the withstand voltage Vbr (V), and the vertical axis is the number η of the retaining rings. This paper size is applicable to China National Standard (CNS) A4 specification (210 × 297 mm) 47-544932 A7 B7 V. Description of the invention (15) (Please read the precautions on the back before filling this page) n_ drift used in experiments The characteristics of the layer, the characteristics of the wafer containing phosphorus with Si resistivity p = 18 Ω cm, thickness t = 48.5 // m of Si (bl line), and p = 32.5Qcm, t = 76.5 // m Si (b2 line) two types. With each wafer, the withstand voltage Vbr increases as the number of guard rings increases. However, about 97 to 98% of the theoretical withstand voltage (654V and 1011V, respectively) in the case of a plane junction calculated from the Si characteristics of the 11_drift layer is saturated, and even if the number of guard rings is increased, Does not change. The number η of the guard rings and the boundary where the pressure resistance is rapidly increased is completed by the formula (line b3) of n = l.CUVbi7100. In addition, it is shown that the relationship between the number of pressure-retaining grommets which hardly causes an increase in withstand voltage even when the number of the grommets is increased is n = 1.5xVbr / 100 (b4 line). Since the pressure-resistant structure of the conventional technology is limited to about 90% of the plane-joint withstand voltage calculated from the above-mentioned Si characteristics, the effect of the high pressure-resistance can be expected by the number of the above-mentioned guard rings represented by the above formula. On the other hand, the upper limit of η is set to 6. (UVbr / 100 or less. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. If the number of guard rings is increased, the pressure-resistant structure will become wider. Disadvantages of increasing the size. As shown in FIG. 14, the pressure limit is saturated even if the number of retaining rings is increased. Therefore, it is practical to set an upper limit for the number of retaining rings. The tolerance of the charge storage effect on the surface of the withstand voltage structure is assumed to be approximately 6 times the number of the guard rings of the relationship in which the effects of the present invention begin. That is, the relationship is n = 6. Ox Vbr / 1 00. By The number of guard rings below this relationship can prevent the charge storage effect on the surface of the device, and at the same time can achieve a small chip size and high withstand voltage. ___________ --- This paper size applies to China National Standard (CNS) Α4 specifications ( 210 × 297 mm) 544932 A7 B7 V. Description of the invention (16) (Please read the precautions on the back before filling this page) Second, make the second conductive well area and the first one from the side of the second conductive well area. Second conductivity type The interval between the rings is 1 // m or less, preferably 0.5 # m or less. The interval obtained by the two-dimensional simulation and the test device for changing the interval between the second conductive type well region and the first second conductive type guard ring. The relationship with the withstand voltage Vbr (V) is shown in Figure 15. The horizontal axis is the interval (// m), and the vertical axis is the withstand voltage Vbr (V). At this time, the characteristic of the n_drift layer is p = 22.5 Ω cm Si with thickness t = 57.0 // m. The joint depth of the p-well region and the retaining ring is 3.5 // m. With the separation from the P-well region to the retaining ring, the pressure drops monotonously, at 3 // The pressure resistance (line C2) of the combination of the m η · drift layer and the conventional pressure-resistant structure is approximately the same. As shown in FIG. 15, by making the interval between the p-well region and the first guard ring less than 1 // m, It can ensure that the pressure resistance of the ιΓ drift layer is more than about 95% (c 1 line), which can also increase the pressure resistance by 5% compared to the conventional structure (c 2 line). Furthermore, if the ρ well region and the first The spacing of the guard rings is 0.5 / m or less, and the withstand voltage is about 7.5% higher than the conventional structure. The relationship between the on-resistance and the withstand voltage printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is known as Ron 〇 〇Vbr 2 · 5. Therefore, if the interval is less than 0.5 // m, the on-resistance can be reduced by 20%, and the periodical effect can be obtained. In addition, the aforementioned well and the aforementioned first guard ring are on the semiconductor surface. In the case of partial connection, if the connection part of the surface part is empty, the relaxation effect of the electric field strength can have the highest withstand voltage. In addition, the connection between the P-well area and the first guard ring is shown as 0 // m in Figure 15 Until the negative size area where the overlap between the p-well and the retaining ring is displayed, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (17) (Please read the back first Note for this page, please fill in this page again), and saturate around -1 // m. This reason is that if the guard ring is separated from the p-well area, the electric field strength increases due to the curvature shape of the pn junction in the p-well area, and the withstand voltage is reduced. If it is close, the electric field strength of the curvature shape is relaxed. The effect of the curvature of the loop overlap is about 1 # m. Furthermore, the interval between the first and second second conductive guard rings from the side of the second conductive type well region is 1.5 // m or less, preferably 1. 〇 # m or less, more preferably 0.5 // Below m. The relationship between the two-dimensional simulation of changing the interval between the first and second second conductivity type guard rings and the interval obtained with the pilot device and the withstand voltage Vbr (V) is shown in FIG. 16. The horizontal axis is the interval (// m), and the vertical axis is the pressure resistance vbi * (V). The interval between the P well area and the first guard ring is 0.5. // m is represented by the d 1 line 'is 1 · 0 // m is represented by the d 2 line and is 1 · 5 // m is represented by the d 3 Line representation. An important item to be obtained for the guard rings after the second step is how to not reduce the withstand voltage set in the first guard ring. Therefore, by setting the interval between the first and second guard rings to 1.5 / z m or less, it is possible to ensure that the withstand pressure determined by the relationship between the p-well and the first guard ring is about 98% or more. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs below 1.0 // m and below 0.5 // m, it is possible to ensure a pressure-resistant structure of 99% or more and approximately 99.5% or more, respectively. The reason is the same. As the distance between the first guard ring and the second guard ring is reduced, the electric field strength at the joint portion with the voltage support layer can be reduced, and high withstand voltage becomes possible. In addition, the distance between the second and third second conductivity type retaining rings from the side of the second conductivity type well area is 2.0 // m or less, preferably 1.0 // m or less. This paper size applies to the country of China Standard Race (CNS) Α4 Specifications (210 × 297 mm)-544932 Α7 _____ Β7 V. Invention Description (18) 〇 (Please read the precautions on the back before filling this page) About changing the second and third second conductive The relationship between the two-dimensional simulation of the gap between the retaining rings and the pressure obtained by the trial device is not squarely ^ Table 1. The parameter is the interval between the first conductive well region and the first second conductive ring. Let the interval between the first and the second second conductivity type guard ring be i .〇 // m 〇 [Table 1] " --------- The distance between the three guard rings and the wear-resistant P-well area Vbr (V) combination with the first and second and withstand voltage pair li and the second and third of the first and second of I2 interval interval interval ratio (%) li (// m) h ( β m) h (μ m) 0.5 1.0 1.0 738 99.6 0.5 1.0 2.0 737 99.4 1.0 1.0 1.0 732 99.6 1.0 1.0 2.0 730 99.3 Any printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs shall be made by ordering Articles 2 and Η The spacing of the guard rings is less than 2.0 // m ', which can ensure that the pressure resistance of the ρ well and the first guard ring determined by the first and second guard rings is more than 99%. If it is 1.0 e m or less, the above-mentioned withstand voltage can be as high as about 99.5% or more. These are the same as those described above, and it is possible to reduce the electric field strength at the joint portion and make it possible to increase the withstand voltage. If the third second conductive type retaining ring and the fourth second conductive type retaining ring are made to the paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm f --- 544932 A7 B7 employees of the Intellectual Property Bureau of the Ministry of Economy Printed by the Consumer Cooperative 5. The interval of the invention description (19) is 2.5 // m or less, preferably 2.0 // m or less, which can also relax the electric field strength of the joint part and make high withstand voltage possible. When the second When the depth of joint between the conductive type parallel region and the second conductive type guard ring is shallow, the aforementioned second conductive type well region and the first second conductive type guard from the side of the second conductive type well region are made. The interval between the rings is d! / 4 or less, preferably ch / 8 or less. These slightly change the view and define the second conductive well area based on the joint depth of the second conductive well area or the second conductive guard ring. The distance from the first and second conductive type guard ring. As before, the electric field strength of the joint portion can be relaxed to make high withstand voltage possible. When the bonding depth of the second conductive type guard ring is d2, the first One second conductive guard ring and second second guide The distance between the two type guard rings is d2 / 4 or less, preferably d2 / 8 or less. Furthermore, the distance between the second second conductive type guard ring and the third second conductive type guard ring is d2 / 4 or less, It is preferably d2 / 8 or less. These also change the view, and specify the first second conductive type guard ring and the second second conductive type guard ring, or the second based on the joint depth of the second conductive type guard ring. The distance between each second conductive type guard ring and the third second conductive type guard ring. As mentioned above, the electric field strength of the joint portion can be relaxed to make high withstand voltage possible. When the second conductive type well area is made the same as the first When the interval between the second conductive type guard ring is h, and when the distance between the first second conductive type guard ring and the second second conductive type guard ring is 12, let l2-h be less than 1 // m, and when the first The distance between each second conductive type guard ring and the second second conductive type guard ring is h, the second second (please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specifications (210X 297 mm) 22 544932 A7 B7 V. Description of the invention (20) (Please read the precautions on the back before filling in this Page) When the distance between the conductive guard ring and the third second conductive guard ring is 13, let 13-12 be 1 // m or less. Furthermore, when the second second conductive guard ring and the third When the interval between the second conductive type guard ring is h, and when the distance between the third second conductive type guard ring and the fourth second conductive type guard ring is 14, let Uh be 1 // m or less. This also changes. In the view, if the two adjacent intervals are too different, the electric field strength will rise and fall in a large part. To avoid this phenomenon, at least to the vicinity of the fourth guard ring, the difference between the adjacent two intervals is 1 / / m or less. However, if the difference between the set intervals is 1 2-1 1, 1 3-1 2, 1 4-1 3 is smaller than 0.5 5 // m, although the effect of reducing the withstand voltage has the effect, The smaller the potential difference between the guard rings, the worse the dimensional efficiency, so it is better to be at least 0.2 // m or more, and the difference between the intervals is about 0.5 // m, that is, the range of 0.2 to 0.8 // m is the best. For the case where the number of second conductive type guard rings is large, the width is specified. For example, the width of the first second conductive type guard ring is larger than the width of the fifth second conductive type guard ring, and the second second conductive type The width of the guard ring is larger than the width of the sixth second conductive type guard ring, and the width of the third second conductive type guard ring is larger than that of the seventh second conductive type guard ring. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This can reduce the electric field strength of the inner guard ring, which is higher than the electric field strength near the outer guard ring. Furthermore, on the surface of the voltage support layer between the second conductive type well region and the first second conductive type guard ring, a dielectric film is disposed with a conductive film. By disposing the conductive film in this way, the influence of the charge on the surface of the withstand voltage structure to the semiconductor surface can be shielded, so that a stable withstand voltage can be ensured. In particular, the conductive film is caused to have a floating potential. The above-mentioned effect remains the same even if the aforementioned conductive body is a floating potential. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (21) Conductive film connection. (Please read the precautions on the back before filling out this page) Exactly the same, between the first second conductivity type guard ring and the second second conductivity type guard ring, and the second second conductivity type guard ring and The surface of the aforementioned voltage support layer between the third second conductive type guard ring and the third second conductive type guard ring and the fourth second conductive type guard ring can also be obtained by disposing the dielectric film with the conductive film. Same effect. These conductive films may be made to have a floating potential. The voltage support layer is composed of a semiconductor region of the first conductivity type, a surface side of the semiconductor region of the first conductivity type is a high-resistance layer, and a lower side is composed of a low-resistance layer, and the first conductivity-type semiconductors are alternately arranged The so-called super-junction type of the region and the second conductive type semiconductor region may be used. A protective film made of an organic polymer material film is disposed on the surface of the semiconductor device for protection. The resistivity of the first conductive type surface area arranged and surrounded by the second conductive type well area arranged on the semiconductor surface is printed by the consumer consortium of the Intellectual Property Bureau of the Ministry of Economic Affairs in a region shallower than the aforementioned second conductive type well area. It is better that the resistivity of the voltage support layer is deeper than the second conductive type well region, so that the doping amount of phosphorus ions in the first conductive type surface area is 2x1012 ~ 5x1012cm_2, It is preferably 2.5 × 1012 to 4.0xl012cm-2. According to this, similarly to the above-mentioned reverse doping method, it is effective to reduce the JFET resistance in the surface drain region arranged and surrounded by the second conductivity type well region. Especially in the present invention, because the area ratio of the surface drain region is smaller than the conventional one, the resistance of the IFET is often large, and the effect of the reverse doping is also large. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 544932 A7 B7 V. Description of the invention (22) [Simplified description of the drawing] FIG. 1 shows the n-channel vertical MOSFET according to the first embodiment of the present invention. Substrate table (please read the precautions on the back before filling this page). Fig. 2 is a partial cross-sectional view of an active portion of an n-channel vertical MOSFET of the first embodiment. FIG. 3 is a plan view of a metal electrode of an n-channel vertical MOSFET wafer according to the first embodiment. Fig. 4 is a configuration diagram of the gate electrode and the source electrode of the n-channel vertical MOSFET according to the first embodiment. Fig. 5 is a partial cross-sectional view taken along the line A-A in Fig. 1. Fig. 6 is a characteristic diagram showing the relationship between the surface n-drain region area ratio and Crss and Ron in a trial-produced n-channel vertical MOSFET. Fig. 7 is a characteristic diagram showing the relationship between the width of the main part of the surface n-drain region and Crss and Ron in the trial-produced n-channel vertical MOSFET. FIG. 8 is a characteristic diagram showing the relationship between the length of the surface n-drain region and the Ciss in the trial-produced n-channel vertical MOSFET. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 9 is a characteristic diagram showing the relationship between the length of the surface η-drain region and the Ciss in the trial η-channel vertical MOSFET. FIG. 10 is a characteristic diagram showing the relationship between the length of the surface n-drain region and Ron in a trial-produced n-channel vertical MOSFET. FIG. 11 is a characteristic diagram showing the relationship between the length of the surface n-drain region and Ron in a trial-produced n-channel vertical MOSFET. Fig. 12 is a comparison diagram comparing the relationship between the withstand voltage and RonA in the n-channel vertical MOSFET of the present invention and the comparative example.
j〇JZ 2LO 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（23 ) 圖13係顯示實施例一的η通道縱型MOSFET的耐壓構 造部分之部分剖面圖。 (請先閲讀背面之注意事項再填寫本頁) 圖14係顯示耐壓Vbr與護環條數的關係之特性圖。 圖1 5係顯示p井與第一條護環的間隔與Vbr的關係之 特性圖。 圖1 6係顯示第一條與第二條護環的間隔與Vbr的關係 之特性圖。 圖17係本發明實施例四之η通道縱型MOSFET的主動 部分之部分剖面圖。 圖18係本發明實施例四之η通道縱型MOSFET的主動 部分之部分斜視圖。 圖19係本發明實施例四之η通道縱型MOSFET的耐壓 構造部分之部分剖面圖。 圖20係本發明實施例五之η通道縱型MOSFET的耐壓 構造部分之部分剖面圖。 圖21係本發明實施例六之η通道縱型MOSFET的閘電 極、源電極配置圖。 經濟部智慧財產局員工消費合作社印製 圖22係本發明實施例七之n通道縱型MOSFET的基板 表面之俯視圖。 圖23係本發明實施例七之n通道縱型MOSFET的閘電 極、源電極配置圖。 圖24係本發明實施例八之n通道縱型MOSFET的閘電 極、源電極配置圖。 圖25係本發明實施例九之n通道縱型M0SFEt的基板 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 544932 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（24) 表面之俯視圖。 圖26係實施例九之η通道縱型MOSFET的閘電極、源 電極配置圖。 圖27係沿著圖26的Β-Β線的部分剖面圖。 圖28係本發明實施例十之η通道縱型MOSFET的閘電 極、源電極配置圖。 圖29係本發明實施例十一之η通道縱型MOSFET的耐 壓支持層部分的斜視剖面圖。 圖30係本發明實施例十一之η通道縱型MOSFET的主 要部的部分剖面圖。 圖3 1(a)係本發明實施例Η--之η通道縱型MOSFET的 耐壓構造部分之半導體基板表面的俯視圖，（b)係沿著C-C 線的剖面圖，（c)係沿著D-D線的剖面圖。 圖32係本發明實施例十二之η通道縱型MOSFET的耐 壓支持層部分的斜視剖面圖。 圖33係本發明實施例十三之η通道縱型MOSFET的耐 壓支持層部分的斜視剖面圖。 圖34係本發明實施例十四之η通道縱型MOSFET的耐 壓支持層部分的斜視剖面圖。 圖35(a)係本發明實施例十四之η通道縱型MOSFET的 耐壓構造部分之半導體基板表面的俯視圖，（b)係沿著E-E 線的剖面圖。 圖36係習知的η通道縱型MOSFET的剖面圖。 圖37係習知的η通道縱型MOSFET的一例的閘電極的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）_ ~ ~ (請先閱讀背面之注意事項再填寫本頁)j〇JZ 2LO This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (23) Fig. 13 shows the withstand voltage structure part of the n-channel vertical MOSFET of the first embodiment Partial sectional view. (Please read the precautions on the back before filling this page.) Figure 14 is a characteristic diagram showing the relationship between the withstand voltage Vbr and the number of retaining rings. Fig. 15 is a characteristic diagram showing the relationship between the interval between the p-well and the first guard ring and Vbr. Figure 16 is a characteristic diagram showing the relationship between the distance between the first and second guard rings and Vbr. Fig. 17 is a partial cross-sectional view of an active portion of an n-channel vertical MOSFET according to a fourth embodiment of the present invention. Fig. 18 is a partial perspective view of an active portion of an n-channel vertical MOSFET according to a fourth embodiment of the present invention. FIG. 19 is a partial cross-sectional view of a withstand voltage structure portion of an n-channel vertical MOSFET according to a fourth embodiment of the present invention. FIG. 20 is a partial cross-sectional view of a withstand voltage structure portion of an n-channel vertical MOSFET according to the fifth embodiment of the present invention. FIG. 21 is a configuration diagram of a gate electrode and a source electrode of an n-channel vertical MOSFET according to the sixth embodiment of the present invention. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. FIG. 22 is a top view of the substrate surface of the n-channel vertical MOSFET according to the seventh embodiment of the present invention. Fig. 23 is a layout diagram of the gate and source electrodes of the n-channel vertical MOSFET according to the seventh embodiment of the present invention. Fig. 24 is a configuration diagram of the gate and source electrodes of an n-channel vertical MOSFET according to the eighth embodiment of the present invention. Figure 25 shows the n-channel vertical MOSFEt substrate of the ninth embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). 544932 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Note (24) Top view of the surface. Fig. 26 is a layout diagram of the gate electrode and the source electrode of the n-channel vertical MOSFET according to the ninth embodiment. Fig. 27 is a partial cross-sectional view taken along the line B-B in Fig. 26. Fig. 28 is a layout diagram of the gate and source electrodes of the n-channel vertical MOSFET according to the tenth embodiment of the present invention. FIG. 29 is a perspective cross-sectional view of a voltage-supporting support portion of an n-channel vertical MOSFET according to the eleventh embodiment of the present invention. Fig. 30 is a partial cross-sectional view of a main part of an n-channel vertical MOSFET according to the eleventh embodiment of the present invention. FIG. 3 1 (a) is a plan view of the surface of a semiconductor substrate of the withstand voltage structure portion of the η-channel vertical MOSFET according to the embodiment of the present invention, (b) is a cross-sectional view taken along the CC line, and (c) is taken along the line Sectional view of line DD. Fig. 32 is a perspective sectional view of a voltage-supporting support portion of an n-channel vertical MOSFET according to a twelfth embodiment of the present invention. Fig. 33 is a perspective cross-sectional view of a voltage-supporting support portion of an n-channel vertical MOSFET according to a thirteenth embodiment of the present invention. Fig. 34 is a perspective cross-sectional view of a voltage-supporting support portion of an n-channel vertical MOSFET according to a fourteenth embodiment of the present invention. FIG. 35 (a) is a plan view of the surface of a semiconductor substrate of a withstand voltage structure portion of an n-channel vertical MOSFET according to the fourteenth embodiment of the present invention, and (b) is a cross-sectional view taken along line E-E. FIG. 36 is a cross-sectional view of a conventional n-channel vertical MOSFET. Figure 37 is an example of the gate electrode of a conventional η-channel vertical MOSFET. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ ~ ~ (Please read the precautions on the back before filling this page)
544932 Α7 --- Β7 五、發明説明（25 ) 俯視圖。 圖3 8係習知的η通道縱型MOSFET的其他例的閘電極 的俯視圖。 (請先閱讀背面之注意事項再填寫本頁) 圖39係習知的η通道縱型m〇SFET的再其他例的閘電 極的俯視圖。 Η 40係習知的η通道縱型MOSFET的其他例的剖面圖 〇 Η41係實施例二之^通道縱型；[GBT的主動部分的部分 剖面圖。 圖42係實施例三之η通道縱型IGBT的主動部分的部分 剖面圖。 圖43係顯示試作的^通道縱型MOSFET中的磷離子摻 雜量與Vbr、Ron的關係之特性圖。 【符號說明】 經濟部智慧財產局員工消費合作社印製 11: n +汲極層 11a·. p +汲極層 12: η_漂移層 12a·· ιΓ漂移層的高電阻率部分 12b·· ιΓ漂移層的低電阻率部分 1 3 : ρ井區域 _14、14a、14b、14c、14d: η·表面區域 15·. η +源極區域 16:通道區域 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 56- 544932 A7 B7 五、發明説明（26 ) 17:閘極氧化膜 17a:場氧化膜 (請先閲讀背面之注意事項再填寫本頁) 18:閘電極 19:源電極 2 0:汲電極 21: ρ +接觸區域 22:層間絕緣膜 24:源電極接觸部 26:閘極金屬電極接觸部 27:閘極金屬電極 2 8:源電極墊 29:閘電極墊 3 0:周緣電極 31:凸部 32:閘電極橋 3 3 : ρ周緣區域 34: η反摻雜區域 經濟部智慧財產局員工消費合作社印製 3 5 :場電極 37:聚醯亞胺膜 38:高電阻率區域 4 2:並聯ρ η層 4 2 a: η漂移區域 42b: ρ間隔區域 g、gi〜gw : 護環 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） 59 544932 A7 B7 五、發明説明（27) 【較佳實施例之詳細說明】 (請先閲讀背面之注意事項再填寫本頁) 以下根據添付圖面說明本發明的實施形態。 [實施例一] 圖2係本發明第一實施形態之η通道縱型MOSFET的主 電流流過的主動部分之部分剖面圖。對MOSFET的晶片主 要在周緣區域配設保持耐壓的護環、場電極之所謂的耐壓 構造部分，惟關於此部分於後面敘述。 在低電阻的η+汲極層11上的高電阻率的ιΓ漂移層12的 表面層選擇性地形成Ρ井區域13，在該ρ井區域1 3的內部 形成η +源極區域15。在ρ井區域13之間ιΓ漂移層12的一部 分之η·表面區域14到達表面。21係用以改善接觸電阻的高 雜質濃度的Ρ+接觸區域。 經濟部智慧財產局員工消費合作社印製 在被夾在 η +源極區域15與η_表面區域14的ρ井區域13 的表面上，中介閘極絕緣膜1 7配設多晶矽的閘電極1 8。1 9 係η +源極區域15與ρ +接觸區域21共通接觸的源電極。如此 ，源電極1 9常中介閘電極1 8之上以及形成於側方的層間絕 緣膜22延長於閘電極18上。在η+汲極層11的背面側配設汲 電極20。 簡單地說明此裝置的動作機構。 在阻止狀態下空乏層自與一般接地的源電極1 9等電位 的Ρ井區域13朝漂移層12側擴張，以空乏層的寬度與電 場強度決定的耐壓被確保。空乏層的擴張係由η_漂移層12 本紙張尺度適用中國國家標參（CNS ) Α4規格（210Χ297公釐） 544932 A7 B7 五、發明説明（28 ) 的厚度與電阻率決定，爲了獲得高耐壓，提高電阻率、增 加厚度的話即可。 (請先閲讀背面之注意事項再填寫本頁) 在閘電極1 8若對源電極1 9施加正電位的話，中介閘極 氧化膜17於p井區域13的表面層16形成反轉層，當作通道 (Channel)而動作，電子當作載子（Carrier)由n +源極區域15通 過通道流到η·表面汲極層14，經過rT漂移層12、n +汲極層11 流到汲電極20成爲接通（On)狀態。 圖2的剖面圖與圖36的習知剖面圖非常相似，不同的點 爲P井區域13之間的ιΓ表面區域14的寬度窄。 良好地顯示此實施例一的縱型M0SFET的特徵與其爲 圖i的半導體基板的俯視圖。此外，在圖1因配設於通常的 半導體元件的周緣區域的耐壓構造部與本發明的第一實施 形態的本質無關，故省略。 經濟部智慧財產局員工消費合作社印製 在圖1中p井區域13係包圍延伸於多數個一方向的條狀 rT表面區域14而配置。（此外說明的方便上，省略一部分的 f表面區域14，以點表示。）條狀的η·表面區域14的長度有 數種類係對應圖3的晶片表面的電極配置圖中的源電極1 9、 閘極金屬電極27。在源電極19的寬度爲廣的部分配置長的 條狀ιΓ表面區域14a，在放入閘極金屬電極27的部分配置短 的條狀n_表面區域14b，在配設閘電極墊（Pad)29閘極金屬電 極的寬度廣的部分更成爲短的條狀n_表面區域14c。 在圖3中，在源電極19的內部配設用以和外部端子連接 的源極墊28，包圍源電極1 9而且一部分朝源電極1 9的內部 配置閘極金屬電極27，在朝源電極1 9的內部的閘極金屬電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（29 ) (請先閱讀背面之注意事項再填寫本頁) 極27的一部分配設用以和外部端子連接的閘極墊29。圖3之 中的最外周的周緣電極30係被製作成與汲電極20等電位， 一般爲用以抑制配設於耐壓構造部的最外周的空乏層的擴 張的終止電極（Stopper electrode)。 圖4係顯示成爲作成圖1的半導體表面的各區域之罩幕 之閘電極18的形狀以及閘電極18與源電極接觸部24的相對 配置關係的俯視圖。但是，條的長度係一定的部分。且條 狀的源電極接觸部24與閘電極1 8係交互地配置。延伸於一 方向的閘電極1 8的終端部變細一次後再度擴大。此閘電極 在終端之前變細係爲了使主動區域以外的閘電極面積最小 限，以及因以閘電極18爲罩幕形成p井區域13，藉由受體 (Acceptor)雜質濃度的擴散以儘可能覆蓋前述變細的閘電極 之下，使Crss的降低爲可能。而且，閘電極18的端變寬係 因配設用以與閘極金屬電極的連接的接合部分26。在此接 合部分26之上使圖3的閘極金屬電極27對位。 經濟部智慧財產局員工消費合作社印製 再度回到圖1，在條狀rT表面區域14a、b、c的端的前 面可看到配置被P井區域13包圍的小的ιΓ表面區域14d。此 11_表面區域14d係成爲閘電極18的端的接合部分26下的部分 ，以現在所得到的加工技術的精度爲基礎而決定接合部分 26的尺寸時，爲以p井區域13包圍不完的。若充分地提高 工程加工能力的話，此rT表面區域14d被p井區域13覆蓋而 消滅。 圖5係沿著圖1的A- A線的部分剖面圖。可看到接合部 分26中的閘電極18與閘極金屬電極27的連接樣子。17爲閘極 〇〇 ΌΖΓ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（30 ) 氧化膜、17a爲厚的場氧化膜，19爲源電極。沿著此A-A線 的部分之表面電極上的位置在圖3以A-A線表示。 (請先閱讀背面之注意事項再填寫本頁) 令此實施例一的M0SFET的主要尺寸例爲如以下的値 〇 圖4的閘電極18的寬度爲5.6 // m、長度爲3.6 // m、閘電 極1 8間爲9.4 /z m、即令胞間距（Cell pitch)爲15 // m。以此閘 電極18爲罩幕導入形成p井區域13的雜質。據此，圖1的ιΓ 表面區域14a的寬度爲1.6// m，其間的ρ井區域13的寬度變 成1 3.4 // m。圖2的p井區域1 3的擴散深度約4 // m，n +源極區 域15的寬度爲2.5 // m、擴散深度爲0.3 /z m，圖4的源電極接 觸區域24的寬度爲7/z m。此時，ιΓ表面區域14的面積對半導 體表面中的Ρ并區域13的面積比率約爲0.12。 順便一提，對相同η 表面區域1 4的ρ井區域1 3的面積 之面積比率在習知的圖37、38、39的MOSFET中分別爲約3 、2、1 〇 經濟部智慧財產局員工消費合作社印製 圖13係顯示本實施形態之η通道縱型MOSFET的耐壓 構造部分之部分剖面圖。在圖的左方有主動部，右端爲 MOSFET的端。其一例爲令耐壓等級爲600V。 在n_漂移層12的表面層端部形成ρ周緣區域3 3，在該 表面配設周緣電極30。37係作爲表面保護的聚醯亞胺 (Polyimide)膜。 g!〜gM爲ρ護環。即在源電極19與汲電極電位的周緣電 極30之間配設14條護環。記載於兩條護環之間下方的 數値係以// m單位表示這些護環間的間隔，隨著自源電極 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 63- 544932 A7 B7 五、發明説明（31 ) 19遠離間隔變寬。 (請先閱讀背面之注意事項再填寫本頁) 因耐壓B VDSS = 600V(以下也記爲Vbr)，令n_漂移層12爲 電阻率：12Qcm、厚度50//m。 對耐壓Vbr=600V，護環的數目爲14條。此條數係由規 定先前所述的護環條數η的式l.OxVbr/ΙΟΟ所求出的値，比 1.0x600/100 = 6條還多。 以P井區域13與第一條護環gi的間隔爲0// m連接。第 一條護環以與第二條護環g2的間隔爲0.5// m，以後各護環 間隔依次每 l//m、1.5//m、2//m、2.5//m、3//m、3.5//m 、4/zm、5/zm、6//m、7//m、8//m、9//m 與 0.5 〜l//m 而 變大來設定。而且，護環g的寬度由第一條開始依次以14.5 //m、14.5//m、13.5//m、13.5//m、13.5//m、12.5//m、 12.5//m、11.5//m、10.5//m、10.5//m、10.5//m 、1 0.5 // m、1 0.5 // m使寬度變小而設定。令護環g的深度 與P井區域13相同爲4//m。 經濟部智慧財產局員工消費合作社印製 一般令源電極19爲接地電位，對汲電極20施加正偏壓 (Bias)的情形，空乏層由成爲源極電位的p井區域13與ιΓ漂 移層12間的ρη接合朝η_漂移層12擴張。 在主動部此空乏層由半導體表面的Ρ并區域13朝下側 的漂移層12擴張。 在一方的耐壓構造部分，空乏層除了由Ρ井區域13朝 下側的ιΓ漂移層1 2擴張外，也朝橫方向擴張。對擴張到此 橫方向的空乏層，因護環以〜gw非常接近地設置，故在ρ井 區域13與第一個ρ護環g!之間的半導體表面部分，可抑制 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（32 ) 因P井區域1 3的擴散層具有曲率所造成的形狀效應而增加 的電場強度。同樣地可抑制各護環間的電場強度。 (請先閱讀背面之注意事項再填寫本頁) 藉由上述的設定耐壓變成664V。此可確保電阻率20 Ω cm、η·漂移層的厚度50// m的情形的理論耐壓684 V的97 % 的耐壓。 在習知的耐壓構造，P井區域與ιΓ漂移層之間的pn接 合部分的曲率形狀部分係使耐壓降低的原因，惟藉由在其 附近配置第一個護環，使由P井區域延伸的空乏層簡單地 到達第一個護環，可極端地降低曲率形狀部分的電場強度 〇 同樣的關係因在如第一個護環與第二個護環間、第二 個護環與第三個護環間相鄰的護環間成立，故即使IT漂移 層的電阻率低，高耐壓化也可能。 再者，如果依照 Hu的論文[Rec. Power Electronics Specialists Conf·，San Diego，1979(ΙΕΕΕ，1979)ρ·3 85]等，單 載子裝置的接通電阻Ron已知以 [數3] 經濟部智慧財產局員工消費合作社印製544932 Α7 --- Β7 V. Description of the invention (25) Top view. Fig. 3 is a plan view of a gate electrode of another example of a conventional 8-channel vertical MOSFET. (Please read the precautions on the back before filling out this page.) Figure 39 is a plan view of the gate electrode of still another example of the conventional η-channel vertical MOSFET. Η 40 is a cross-sectional view of another example of a conventional n-channel vertical MOSFET. Η 41 is a ^ -channel vertical of the second embodiment; [partial cross-sectional view of the active part of GBT. Fig. 42 is a partial cross-sectional view of an active portion of a n-channel vertical IGBT of the third embodiment. Fig. 43 is a characteristic diagram showing the relationship between the doped amount of phosphorus ions and Vbr and Ron in the pilot ^ -channel vertical MOSFET. [Symbol description] Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 11: n + drain layer 11a ·. P + drain layer 12: η_drift layer 12a ·· ιΓ High resistivity portion of the drift layer 12b ·· ιΓ Low resistivity part of the drift layer 1 3: ρ well area_14, 14a, 14b, 14c, 14d: η · surface area 15 ·. Η + source area 16: channel area This paper scale applies Chinese National Standard (CNS) A4 specification (210 × 297 mm) 56- 544932 A7 B7 V. Description of the invention (26) 17: Gate oxide film 17a: Field oxide film (Please read the precautions on the back before filling this page) 18: Gate electrode 19: Source Electrode 2 0: Drain electrode 21: ρ + contact area 22: Interlayer insulation film 24: Source electrode contact portion 26: Gate metal electrode contact portion 27: Gate metal electrode 2 8: Source electrode pad 29: Gate electrode pad 3 0 : Peripheral electrode 31: Convex portion 32: Gate electrode bridge 3 3: ρ Peripheral area 34: Printed by the Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs of the η Anti-Doping Region 3 5: Field electrode 37: Polyimide film 38: High Resistivity area 4 2: Parallel ρ η layer 4 2 a: η drift area 42b: ρ interval area g, gi ~ gw: guard ring paper ruler Applicable to China National Standard (CNS) A4 (210X 297 mm) 59 544932 A7 B7 V. Description of the invention (27) [Detailed description of the preferred embodiment] (Please read the precautions on the back before filling this page) The following An embodiment of the present invention will be described with reference to the drawings. [Embodiment 1] Fig. 2 is a partial cross-sectional view of an active portion through which a main current flows of an n-channel vertical MOSFET according to a first embodiment of the present invention. The so-called withstand voltage structure part of the MOSFET chip is mainly provided with a retaining ring and a field electrode in the peripheral region, but this part will be described later. The surface layer of the high-resistance ιΓ drift layer 12 on the low-resistance η + drain layer 11 selectively forms a P-well region 13, and an η + source region 15 is formed inside the p-well region 13. Between the p-well region 13, a part of the? -Drift layer 12? Surface region 14 reaches the surface. 21 is a P + contact region with a high impurity concentration for improving contact resistance. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed on the surface of ρ well region 13 sandwiched between η + source region 15 and η_ surface region 14, intermediary gate insulation film 1 7 with polycrystalline silicon gate electrode 8 1 9 is a source electrode in which the n + source region 15 and the p + contact region 21 are in common contact. In this way, the source electrode 19 is often interposed on the gate electrode 18 above the gate electrode 18 and formed on the lateral interlayer insulating film 22. A drain electrode 20 is disposed on the back side of the n + drain layer 11. The operation mechanism of this device will be briefly explained. In the blocking state, the empty layer expands from the P-well region 13 which is equipotential to the source electrode 19 which is generally grounded to the drift layer 12 side, and the withstand voltage determined by the width of the empty layer and the electric field strength is ensured. The expansion of the empty layer is determined by the η_drift layer. 12 The paper size is applicable to Chinese National Standards (CNS) A4 specifications (210 × 297 mm) 544932 A7 B7 5. The thickness and resistivity of the invention description (28) are determined. In order to obtain high resistance It is enough to increase the resistivity and increase the thickness. (Please read the precautions on the back before filling this page.) If a positive potential is applied to the source electrode 19 at the gate electrode 18, the intermediary gate oxide film 17 forms a reversal layer on the surface layer 16 of the p-well region 13. Acting as a channel, electrons as carriers flow from the n + source region 15 through the channel to the η · surface drain layer 14, and flow through the rT drift layer 12 and the n + drain layer 11 to the drain. The electrode 20 is turned on. The cross-sectional view of FIG. 2 is very similar to the conventional cross-sectional view of FIG. 36, and the difference is that the width of the surface region 14 between the P-well regions 13 is narrow. The characteristics of the vertical MOSFET of the first embodiment and the top view of the semiconductor substrate of FIG. I are shown well. In addition, in Fig. 1, the withstand voltage structure portion arranged in the peripheral region of a normal semiconductor element is not related to the essence of the first embodiment of the present invention, and is therefore omitted. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In FIG. 1, the p-well region 13 is arranged around the strip-shaped rT surface region 14 extending in one direction. (In addition, for convenience of explanation, a part of the f-surface area 14 is omitted and indicated by dots.) The length of the stripe η · surface area 14 has a number of types corresponding to the source electrode 19 in the electrode layout diagram of the wafer surface in FIG. Gate pole metal electrode 27. A long strip-shaped surface area 14a is arranged on the wide portion of the source electrode 19, a short strip-shaped n_surface area 14b is arranged on the portion where the gate metal electrode 27 is placed, and a gate electrode pad (Pad) is provided. The wide portion of the 29 gate metal electrode becomes a short stripe n-surface region 14c. In FIG. 3, a source pad 28 is provided inside the source electrode 19 for connection with an external terminal. The source pad 19 surrounds the source electrode 19 and a gate metal electrode 27 is partially disposed inside the source electrode 19. 1 9 The internal gate metal paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (29) (Please read the precautions on the back before filling this page) A part of 27 is provided with a gate pad 29 for connection with an external terminal. The outermost peripheral edge electrode 30 in Fig. 3 is made to have the same potential as the drain electrode 20, and is generally a stopper electrode for suppressing the expansion of an empty layer disposed on the outermost periphery of the pressure-resistant structure portion. Fig. 4 is a plan view showing the shape of the gate electrode 18 and the relative arrangement relationship between the gate electrode 18 and the source electrode contact portion 24 as a mask forming regions of the semiconductor surface of Fig. 1. However, the length of the bar is a certain part. The strip-shaped source electrode contact portions 24 are arranged alternately with the gate electrode 18 series. The terminal portion of the gate electrode 18 extending in one direction is narrowed once and then enlarged again. The thinning of the gate electrode before the termination is to minimize the area of the gate electrode outside the active area, and to form the p-well region 13 with the gate electrode 18 as a mask. Covering the aforementioned thinned gate electrode makes it possible to reduce Crss. Further, the widening of the end of the gate electrode 18 is due to the provision of a joint portion 26 for connection with the gate metal electrode. The gate metal electrode 27 of FIG. 3 is aligned on this joint portion 26. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Returning to FIG. 1 again, a small surface area 14d surrounded by a P-well area 13 can be seen in front of the ends of the strip-shaped rT surface areas 14a, b, and c. The 11_surface region 14d is a portion below the joint portion 26 which is the end of the gate electrode 18. When the size of the joint portion 26 is determined based on the accuracy of the processing technology obtained at present, it is endlessly surrounded by the p-well region 13. . If the engineering processing capacity is sufficiently improved, the rT surface area 14d is covered by the p-well area 13 and then eliminated. Fig. 5 is a partial cross-sectional view taken along the line A-A of Fig. 1. The connection between the gate electrode 18 and the gate metal electrode 27 in the joint portion 26 can be seen. 17 is the gate electrode 〇〇 ΌZΓ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (30) An oxide film, 17a is a thick field oxide film, and 19 is a source electrode. The position on the surface electrode of the part along the A-A line is shown by the A-A line in FIG. 3. (Please read the precautions on the back before filling this page) Let the example of the main dimensions of the M0SFET of the first embodiment be as follows. The width of the gate electrode 18 in FIG. 4 is 5.6 // m and the length is 3.6 // m The gate electrode 18 is 9.4 / zm, that is, the cell pitch is 15 // m. The gate electrode 18 is used as a mask to introduce impurities forming the p-well region 13. Accordingly, the width of the ιΓ surface region 14a in FIG. 1 is 1.6 // m, and the width of the ρ well region 13 therebetween becomes 1 3.4 // m. The p-well region 13 in FIG. 2 has a diffusion depth of about 4 // m, the width of n + source region 15 is 2.5 // m, and the diffusion depth is 0.3 / zm. The width of the source electrode contact region 24 in FIG. 4 is 7 / zm. At this time, the area ratio of the area of the ιΓ surface region 14 to the area of the PD region 13 in the semiconductor surface is about 0.12. By the way, the area ratio of the area of the p-well region 13 to the same η surface region 14 is about 3, 2, 10 in the conventional MOSFETs of FIGS. 37, 38, and 39, respectively. Printed by the consumer cooperative FIG. 13 is a partial cross-sectional view showing a withstand voltage structure portion of the n-channel vertical MOSFET of this embodiment. There is an active part on the left of the figure, and the right end is the end of the MOSFET. One example is to make the withstand voltage level 600V. A ρ peripheral region 33 is formed at the end of the surface layer of the n_drift layer 12, and a peripheral electrode 30 is disposed on the surface. 37 is a polyimide film as a surface protection. g! ~ gM are ρ guard rings. That is, 14 guard rings are arranged between the source electrode 19 and the peripheral electrode 30 of the potential of the drain electrode. The number recorded between the two guard rings indicates the interval between these guard rings in the unit of // m. With the source electrode, the paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 63 -544932 A7 B7 V. Description of the invention (31) 19 The distance is widened away. (Please read the precautions on the back before filling this page.) Since the withstand voltage B VDSS = 600V (hereinafter also referred to as Vbr), let n_drift layer 12 be resistivity: 12Qcm, thickness 50 // m. For the withstand voltage Vbr = 600V, the number of guard rings is 14. This number is determined by the formula l.OxVbr / ΙΟΟ which specifies the number η of the retaining rings previously described, which is more than 1.0x600 / 100 = 6. The P-well region 13 is connected to the first guard ring gi at an interval of 0 // m. The distance between the first grommet and the second grommet g2 is 0.5 // m, and the spacing of each subsequent grommet is 1 // m, 1.5 // m, 2 // m, 2.5 // m, 3 / / m, 3.5 // m, 4 / zm, 5 / zm, 6 // m, 7 // m, 8 // m, 9 // m, and 0.5 to 1 // m are set to be larger. Moreover, the width of the grommet g is 14.5 // m, 14.5 // m, 13.5 // m, 13.5 // m, 13.5 // m, 12.5 // m, 12.5 // m, 11.5 // m, 10.5 // m, 10.5 // m, 10.5 // m, 1 0.5 // m, 1 0.5 // m are set to make the width smaller. Let the depth of the grommet g be the same as that of the P-well region 13 to be 4 // m. In the case of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the source electrode 19 is generally grounded, and a positive bias (Bias) is applied to the drain electrode 20. The empty layer consists of the p-well region 13 and the ιΓ drift layer 12 that become the source potential. The indirect ρη junction expands toward the η_drift layer 12. This empty layer in the active portion expands from the P region 13 on the semiconductor surface toward the drift layer 12 on the lower side. In one part of the pressure-resistant structure, the empty layer expands in the horizontal direction in addition to expanding from the P-well region 13 to the ιΓ drift layer 12 on the lower side. For the empty layer expanded to this horizontal direction, since the guard ring is arranged very close to ~ gw, the semiconductor surface portion between the ρ well region 13 and the first ρ guard ring g! Can suppress the application of this paper to China. National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (32) The electric field strength increased due to the shape effect caused by the curvature of the diffusion layer 13 in the P-well region 13. In the same way, the electric field strength between the guard rings can be suppressed. (Please read the precautions on the back before filling this page.) With the above setting, the withstand voltage becomes 664V. This ensures a withstand voltage of 97% of the theoretical withstand voltage of 684 V in the case of a resistivity of 20 Ω cm and a thickness of the η · drift layer of 50 // m. In the conventional pressure-resistant structure, the curvature shape part of the pn junction between the P-well region and the ιΓ drift layer is the reason for reducing the pressure resistance. However, the first guard ring is arranged near the The empty layer of the area extension simply reaches the first guard ring, which can extremely reduce the electric field strength of the curvature shape part. The same relationship is due to the relationship between the first guard ring and the second guard ring, and the second guard ring and The third guard ring is established between adjacent guard rings, so even if the resistivity of the IT drift layer is low, high withstand voltage is possible. Furthermore, if according to Hu's paper [Rec. Power Electronics Specialists Conf., San Diego, 1979 (ΙΕΕΕ, 1979) ρ · 3 85], etc., the on-resistance Ron of the single-carrier device is known to be [num. 3] economical. Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative
Ron〇〇 (Vbr)2·5 表示，與耐壓Vbr的2.5次方成比例。 即若耐壓提高1%的話，（因相同的電阻率可使用厚度薄 的晶圓）接通電阻可降低約2.5%。因此，具有耐壓5%的提高 與接通電阻的約13%的降低有關，具有耐壓7.5%的提高、接 通電阻20 %的大幅降低之劃期的效果。 此處，附加關於令P井區域13與第一條護環gl的間隔 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 3& 544932 A7 B7 五、發明説明（33) 爲0 // m而連接的意思。 (請先閱讀背面之注意事項再填寫本頁) 因p井區域1 3與第一條護環g!以間隔爲〇 # m連接，故 第一條護環g 1可考慮乍看之下像是無意思，惟如圖1 5可見 到的，這些P井區域1 3與第一條護環g!連接，或即使重合 也會帶來耐壓的提高。 P井區域13與第一條護環21的間隔爲O/zm有另一個的 意思。在用以形成P井區域13與第一條護環gi的雜質導入 用罩幕中’藉由使迫些P井區域1 3與第一條護環g!的間隔 爲0而放置，假如即使因製程的偏差而有0.5 // m以下的過度 蝕刻（Over-etching)，p井區域13與第一條護環gl的間隔也能 被抑制到〇· 5 // m以下。如此，具有補償某種程度的製程偏 差之效果。 試作耐壓等級不同的M0SFET，與圖39的習知M0SFET 比較。圖1 2係比較耐壓與RonA的關係的特性比較圖。橫軸 爲耐壓BVdss (V)、縱軸爲接通電阻RonA(mQ cm2)，任何圖 都以對數表示。 經濟部智慧財產局員工消費合作社印製Ron〇〇 (Vbr) 2.5 indicates that it is proportional to the 2.5th power of the withstand voltage Vbr. That is, if the withstand voltage is increased by 1%, (on the basis of the same resistivity, a thin wafer can be used), the on-resistance can be reduced by about 2.5%. Therefore, a 5% increase in withstand voltage is related to a reduction of about 13% in the on-resistance, a schedule effect of an increase in withstand voltage of 7.5% and a significant reduction in on-resistance of 20%. Here, the space between the P-well area 13 and the first guard ring gl is attached. The paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 3 & 544932 A7 B7 V. Description of the invention (33) is 0 // m while connected. (Please read the precautions on the back before filling in this page) Because the p-well area 1 3 is connected to the first guard ring g! At an interval of 0 # m, the first guard ring g 1 can be considered at first glance. It is meaningless, but as can be seen in Figure 15, these P well regions 13 are connected to the first grommet g !, or even if they overlap, it will increase the pressure resistance. The interval between the P-well region 13 and the first guard ring 21 is O / zm, which has another meaning. In the mask for introducing impurities for forming the P-well region 13 and the first guard ring gi 'is placed by forcing the interval between the P-well regions 13 and the first guard ring g! To be 0, if even Due to process deviation, there is over-etching below 0.5 // m, and the interval between the p-well region 13 and the first guard ring gl can also be suppressed to below 0.5 5 m. This has the effect of compensating for some degree of process deviation. The MOSFETs with different withstand voltage levels were tried and compared with the conventional MOSFETs in FIG. 39. Fig. 12 is a characteristic comparison chart comparing the relationship between the withstand voltage and RonA. The horizontal axis is the withstand voltage BVdss (V) and the vertical axis is the on-resistance RonA (mQ cm2). Any graph is expressed in logarithm. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
RonA大致爲習知的一半，得知本發明的功效非常大。 由圖的傾向此功效在未試作的耐壓150V以下中也能期待。 再者關於試作的M0SFET，每三種類的耐壓等級與習知 品比較接通電阻與閘極/汲極間電容的積[Ron · Crss]，整理 於表2。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（34) [表2]RonA is about half of the conventional one, and it is learned that the efficacy of the present invention is very large. From the tendency of the figure, this effect can be expected even at a withstand voltage of 150V or less that has not been tried out. In addition, for the trial M0SFETs, the product of the on-resistance and the gate / drain capacitance [Ron · Crss] for each of the three types of withstand voltage levels compared with conventional products is summarized in Table 2. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of invention (34) [Table 2]
耐壓（V) 170 660 990 實施例一的 1.8 Ω pF 2.95 Ω pF 1 5.0 Ω pF M0SFET 習知M0SFET 8.8Ω pF 17.5 Ω pF 80 Ω pF (請先閱讀背面之注意事項再填寫本頁)Withstand voltage (V) 170 660 990 Example 1 1.8 Ω pF 2.95 Ω pF 1 5.0 Ω pF M0SFET Known M0SFET 8.8 Ω pF 17.5 Ω pF 80 Ω pF (Please read the precautions on the back before filling this page)
Ron· Crss都爲習知的1/5左右。 裝置的損失係以接通電阻與開關損失決定，因Crss越 小開關損失越小，故[Ron · Crss]積小的裝置其損失小。得 知此特性本發明品也比習知品還大幅地小，效果非常大。 若擴張閘電極18的寬度，則與圖6的傾向一樣Ron的變 動幾乎沒有的 Crss增大，開關損失變大。相反地若縮小聞 電極18的寬度則Crss降低，惟Ron增大穩定損失變大。 經濟部智慧財產局員工消費合作社印製 沿著延伸於一方向的閘電極的一方向的長度在實施例 一大約等於晶片的主電流流過的主動部的尺寸，4mm左右 。此長度爲大約等於晶片的主動部的尺寸的長度也可以， 惟爲了不增加內部閘電阻，以1 00 // m以上較佳爲500 // m以 上的間隔配設與閘電極連接的部分當然也沒關係。 此外，得知圖2的剖面圖大致與圖36的習知構造相同， 實施例一的M0SFET的製程大致與習知的相同也可以，然 而只能藉由改變圖案來實現。 圖4 1係本發明的第二實施形態之n通道縱型ig BT的主 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210X297公釐） 544932 Α7 Β7 五、發明説明（35) (請先閲讀背面之注意事項再填寫本頁) 電流流過的主動部分的部分剖面圖。對於IGBT的晶片主要 在周緣區域配設保持耐壓的護環、場電極之所謂的耐壓構 造部分，惟關於此部分於後面敘述。 在低電阻的P +汲極層11a上的高電阻率的n_漂移層12的 表面層選擇性地形成P井區域13，在該p井區域13的內部 形成n +源極區域15。在p井區域13之間n_漂移層12的一部 分之n_表面區域14到達表面。 在被夾在n +源極區域15與n_表面區域14的p井區域13 的表面上，中介閘極絕緣膜17配設多晶矽的閘電極18。19 係n +源極區域15與p +接觸區域21共通接觸的源電極。如此 ，源電極19常中介閘電極18之上以及形成於側方的層間絕 緣膜22延長於閘電極18上。在p +汲極層11a的背面側配設汲 電極20。 半導體表面的俯視圖、閘電極的接觸、金屬電極等與 實施例一的圖1、4、3完全相同也可以。 與實施例一的MOSFET不同的點爲剖面構造，汲電極 20所接觸者爲p +汲極層11a而不是n +汲極層。 經濟部智慧財產局員工消費合作社印製 動作爲藉由給予閘電極1 8的訊號控制由汲電極20流到 源電極19的電流係相同，惟因電洞（Hole)自p +汲極層11植入 η —漂移層12，故變成雙載子模式，接通電阻比M0SFET還低 〇 在此IGBT中接通電阻也比習知的IGBT約被降低30% OQ 〇〇 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 544932 A7 B7 五、發明説明（36 ) [實施例三] (請先閱讀背面之注意事項再填寫本頁) 圖42係本發明的第三實施形態之η通道縱型IGBT的主 電流流過的主動部分的部分剖面圖。 與圖41的實施例二的IGBT之不同點爲ιΓ漂移層係由高 電阻率部分1 2 a與低電阻率部分12 b所構成。 因藉由低電阻率部分1 2b，逆電壓施加時的空乏層的擴 張被限制，故具有可使高電阻率部分1 2a的厚度變薄的優點 〇 因此，在n_漂移層的電壓下降被降低，可當作接通電 阻可比實施例二的IGBT還更低的IGBT。 [實施例四] 圖17係本發明第四實施形態之η通道縱型MOSFET的 主動部分之部分剖面圖。圖1 8係斜視圖。 與實施例一的縱型MOSFET的圖2之不同點爲在主動部 中的兩個p井區域13間的11_表面區域14處形成η反摻雜區 域34。 經濟部智慧財產局員工消費合作社印製 η反摻雜區域34例如藉由劑量爲2.5Χ1012〜4.Oxl 012cnT2的 憐離子植入以及熱處理形成。深度約4 // m。 圖43係顯示磷離子的劑量與耐壓Vbr以及接通電阻 Ron的關係。橫軸爲劑量、縱軸爲Vbr或Ron。在圖43中， 磷離子的劑量爲2.5xl012cm·2以上的Ron爲幾乎不變的値， 惟在2.0xl012cm_2以下，R0n急遽地增大。而且，磷離子的劑 量爲4.0xl012cm·2以下的 Vbr爲幾乎不變的値，惟在 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 3^ 544932 A7 B7 五、發明説明（37 ) (請先閲讀背面之注意事項再填寫本頁) 5.0xl012cm_2以上，Vbr急遽地下降。而且，即使在Vgs = -30V ，在4.4xl012cm_2以上Vbr急遽地下降。由這些結果劑量爲 2.0乂1012〜5.(^1〇12(：111-2較佳爲2.5乂1012〜4.(^1012(：111-2的範圍。 藉由形成此η反摻雜區域34，使以被p井區域13包圍 的表面汲極區域構成的JFET電阻降低，串聯電阻部分被降 低，與接通電阻的降低有關。Ron · Crss is about 1/5 of the conventional one. The loss of the device is determined by the on-resistance and the switching loss. The smaller the Crss is, the smaller the switching loss is. Therefore, the device with a small [Ron · Crss] product has a small loss. Knowing this characteristic, the product of the present invention is also significantly smaller than the conventional product, and the effect is very large. When the width of the gate electrode 18 is expanded, the Crss with almost no change in Ron increases as in the tendency of Fig. 6, and the switching loss increases. Conversely, if the width of the electrode 18 is reduced, Crss decreases, but Ron increases to increase the stability loss. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The length of one direction of the gate electrode extending in one direction in the first embodiment is approximately equal to the size of the active part through which the main current of the chip flows, about 4 mm. This length may be approximately equal to the size of the active part of the chip, but in order not to increase the internal gate resistance, it is necessary to arrange the part connected to the gate electrode at an interval of 1 00 // m or more, preferably 500 // m or more. does not matter. In addition, it is learned that the cross-sectional view of FIG. 2 is substantially the same as the conventional structure of FIG. 36. The manufacturing process of the MOSFET of the first embodiment may be substantially the same as the conventional one, but it can only be realized by changing the pattern. Figure 1 1 The main paper size of the n-channel vertical ig BT according to the second embodiment of the present invention is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 Α7 Β7 5. Description of the invention (35) (please (Please read the precautions on the back before filling out this page) Partial cross-sectional view of the active part through which the current flows. The IGBT chip is mainly provided with a so-called withstand voltage structure part for retaining a withstand voltage and a field electrode in a peripheral region, but this part will be described later. A surface layer of the high-resistance n_drift layer 12 on the low-resistance P + drain layer 11a selectively forms a P-well region 13, and an n + -source region 15 is formed inside the p-well region 13. Between the p-well region 13 a part of the n_drift layer 12 reaches the surface 14. On the surface of the p-well region 13 sandwiched between the n + source region 15 and the n_ surface region 14, an intermediary gate insulating film 17 is provided with a gate electrode 18 of polycrystalline silicon. 19 The n + source region 15 and p + The contact regions 21 share a common source electrode. In this way, the source electrode 19 is often extended on the gate electrode 18 through the gate electrode 18 and the interlayer insulating film 22 formed on the side. A drain electrode 20 is disposed on the back side of the p + drain layer 11a. The plan view of the semiconductor surface, the contact of the gate electrode, the metal electrode, and the like may be the same as those in Figs. 1, 4, and 3 of the first embodiment. A point different from the MOSFET of the first embodiment is the cross-sectional structure, and the contact of the drain electrode 20 is the p + drain layer 11a instead of the n + drain layer. The employee ’s consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has the same brake control as the current flowing from the drain electrode 20 to the source electrode 19 by the signal given to the gate electrode 18, but the hole (Hole) from p + drain layer 11 The η-drift layer 12 is implanted, so it becomes a two-carrier mode, and the on-resistance is lower than M0SFET. In this IGBT, the on-resistance is also reduced by about 30% compared to the conventional IGBT. OQ 〇〇 This paper is applicable to China Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (36) [Example 3] (Please read the notes on the back before filling this page) Figure 42 shows the third embodiment of the present invention. A partial cross-sectional view of an active portion through which a main current of an n-channel vertical IGBT flows. The difference from the IGBT according to the second embodiment in FIG. 41 is that the drift layer is composed of a high resistivity portion 12a and a low resistivity portion 12b. Since the expansion of the empty layer when the reverse voltage is applied is limited by the low resistivity portion 12b, there is an advantage that the thickness of the high resistivity portion 12a can be reduced. Therefore, the voltage drop in the n_drift layer is reduced. The reduction can be regarded as an IGBT whose on-resistance can be lower than that of the IGBT of the second embodiment. [Fourth Embodiment] Fig. 17 is a partial cross-sectional view of an active portion of an n-channel vertical MOSFET according to a fourth embodiment of the present invention. Figure 18 is a perspective view of the 8 series. The difference from FIG. 2 of the vertical MOSFET of the first embodiment is that an n-doped region 34 is formed at an 11-surface region 14 between two p-well regions 13 in the active portion. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the η anti-doped region 34 is formed by, for example, implantation and heat treatment of ions at a dose of 2.5 × 1012 to 4.Oxl 012cnT2. The depth is about 4 // m. Figure 43 shows the relationship between the dose of phosphorus ions, the withstand voltage Vbr, and the on-resistance Ron. The horizontal axis is the dose and the vertical axis is Vbr or Ron. In Fig. 43, Ron with a dose of 2.5xl012cm · 2 or more is almost unchanged, but Ron increases sharply below 2.0xl012cm_2. In addition, Vbr with a dose of 4.0xl012cm · 2 or less is almost unchanged. However, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applied at this paper size. 3 544932 A7 B7 V. Description of the invention ( 37) (Please read the notes on the back before filling in this page) Above 5.0xl012cm_2, Vbr drops sharply. Moreover, even at Vgs = -30V, Vbr drops sharply above 4.4xl012cm_2. From these results, the dose is 2.0 乂 1012 ~ 5. (^ 1〇12 (: 111-2 is preferably 2.5 乂 1012 ~ 4. (^ 1012 (: 111-2). By forming this n-doped region 34. The JFET resistance formed by the surface drain region surrounded by the p-well region 13 is reduced, and the series resistance portion is reduced, which is related to the reduction of the on-resistance.
在本實施例因減小表面汲極區域的面積比率，故JFET 電阻增大。因此，反摻雜所造成的接通電阻的降低效果大 〇 圖19係第四實施形態之η通道縱型MOSFET的耐壓構 造部之部分剖面圖。與實施例一的縱型MOSFET的圖13之 不同爲對耐壓Vbr = 600V，護環的數目爲6條。 此條數與由規定護環條數η的前述式所求出的 1.0xVbr/100 = 6條相同。 藉由此設定可確保622V與理論耐壓684V的92%的耐壓 。當然護環的條數不增加，耐壓可更高。 經濟部智慧財產局員工消費合作社印製 關於此實施例四的MOSFET，取代n+汲極層以p+汲極 層或藉由配設圖42的低電阻率部分12b與p +汲極層，如實施 例二、三可當作IGBT。關於到以後的實施例十四爲止的 MOSFET的例也一樣，藉由置換n +汲極層可當作IGBT。 [實施例五] 圖20係本發明第五實施形態之η通道縱型MOSFET的 耐壓構造部分之部分剖面圖。 與實施例一的縱型MOSFET的圖13之不同點爲護環的 4Θ- 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 544932 Α7 Β7 五、發明説明（38) 數目爲六條，以及在兩個P護環之間的場氧化膜1 7a上形成 導電體的多晶矽膜的場電極35。 (請先閲讀背面之注意事項再填寫本頁) 裝置（Device)在實際使用狀態下，在汲電極20、源電極 19間施加電壓。給予長期的電壓施加時的可靠度影響的項 目有裝置表面的電荷儲存效應。若在耐壓構造部兩端的電 極間也被施加電壓的話，在耐壓構造部的表面電荷被感應 ，中介絕緣層給予半導體表面特別是ιΓ漂移層12的表面部 分影響，擾亂半導體內部的電場與耐壓劣化有關。 在此例藉由於耐壓構造部的層間絕緣膜22與ιΓ漂移層 1 2的表面的場氧化膜1 7a表面的中間配設多晶矽膜的場電極 3 5，可利用靜電遮蔽效應抑制表面電荷的影響。此外，在 主動部因源電極19與閘電極18覆蓋ιΓ漂移層表面，故成爲 不受表面電荷影響的構造。 經濟部智慧財產局員工消費合作社印製 即藉由在Ρ井區域13與第一個護環。之間以及護環間 的η_表面區域14，中介場氧化膜17a配置導電體的多晶矽膜 之場電極35，可防止表面電荷儲存效應，可期待可靠度上 的效果。耐壓大致與實施例二相同。此外，令場電極35的 電位爲浮置，惟也能配設電位給予適當的電位。 [實施例六] 圖21係顯示本發明第六實施形態之η通道縱型MOSFET 的源電極接觸部24與閘電極1 8的相對配置關係圖。令耐壓 構造部與實施例——樣。 與實施例一的圖4所說明的構造的不同點爲除了在條狀 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 44 544932 A7 B7 五、發明説明（39 ) (請先閲讀背面之注意事項再填寫本頁) 的聞電極1 8的兩端外’其中間也配設與聞極金屬電極的接 合部分26。據此，對於內部閘電阻的降低以及接通電阻的 增加抑制具有效果。 藉由在一半長度的條狀閘電極1 8的各個端配設接合部 分26，使實施例六的構造可提高主動部面積的效率。 半導體基板表面的俯視圖在途中n_表面區域1 4被中斷 ，小的n_表面區域被夾住。若加工精度高的話，可消除該 小的n_表面區域。 在此實施例六，與閘極金屬電極的接合部分26僅於閘 電極1 8的中間配設一個位置，惟當然也能對延伸於同樣的 一方向的閘電極配設複數個位置。 [實施例七] 圖22係顯示本發明第七實施形態之η通道縱型MOSFET 的半導體基板的俯視圖。此外，圖22與圖2—樣省略耐壓構 造部而顯示。令耐壓構造部與實施例——樣。 經濟部智慧財產局員工消費合作社印製 在此例，η_表面區域14(以點省略有複數個而顯示）基本 上與實施例一的圖1一樣，被Ρ井區域13包圍呈現延伸於一 方向的形狀。與圖2的不同點爲表面區域14延伸於一方向 ，且在對延伸的方向大槪垂直的方向具有複數個凸部3 1。 此凸部3 1的配置頻率被設定爲大約每250 // m —個，而 且，對此凸部31的ιΓ表面區域14的延伸方向與垂直方向之 尺寸爲約0.5 // m。 圖23係顯示成爲作成圖22的半導體表面的各區域之罩 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 Α7 Β7 五、發明説明（4〇) 幕之閘電極1 8的形狀以及閘電極1 8與源電極接觸部24的相 對配置關係的俯視圖。 (請先聞讀背面之注意事項再填寫本頁) 圖23的形狀與圖4的形狀之不同點爲在延伸於一方向的 閘電極18，於對延伸的方向垂直地配設閘電極的橋 (Bridge)32。此閘電極的橋32的頻率被設定爲大約每250 // m 一個，而且，此閘電極橋32的寬度被設定爲2.5// m。 若藉由以此閘電極1 8爲罩幕導入雜質，形成p井區域 1 3的話，因對p井區域1 3的表面橫方向的擴散以2 // m設計 ，閘電極的橋32之下與來自橋32兩側的擴散區域連接，故 變成一條P井區域13。但是，因在橋32的根下的部分不與 來自兩側的擴散區域連接，故殘留n_表面區域的凸部31。 在此例子，因閘電極18被橋32連接，故閘電阻被降低 ，接通電阻也被降低。 [實施例八] 經濟部智慧財產局員工消費合作社印製 圖24係顯示本發明第八實施形態之η通道縱型MOSFET 的閘電極18以及閘電極18與源電極接觸部24的相對配置關 係的俯視圖。令耐壓構造部與實施例一 一樣。 與實施例七的圖23所說明的構造的不同點爲除了在條 狀的閘電極1 8的兩端外，其中間也配設與閘極金屬電極的 接合部分26。 據此，對於內部閘電阻的降低以及接通電阻的增加抑 制具有效果。藉由在一半長度的條狀閘電極1 8的各個端配 設接合部分26，使實施例八的構造可提高主動部面積的效 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 4^ 544932 Α7 Β7 五、發明説明（41 ) 率。 (請先閱讀背面之注意事項再填寫本頁) 半導體基板表面的俯視圖在途中η·表面區域14被中斷 ，小的ιΓ表面區域被夾住。若加工精度高的話，可消除此 rT表面區域14 d。 與此閘極金屬電極的接合部分在此實施例八，當然雖 然僅於延伸於一方向的閘電極的中間配設一個位置，惟同 樣的構造也能對延伸於一方向的閘電極配設複數個位置。 [實施例九] 圖25係顯示本發明第九實施形態之η通道縱型MOSFET 的半導體基板表面的俯視圖。在圖25與實施例——樣省略 耐壓構造部而顯示。令耐壓構造部與實施例——樣。 在圖25中，η_表面區域14係延伸於一方向的條狀，複數 個（以點省略有複數個而顯示）係平行地配置，以Ρ井區域13 包圍周圍。 經濟部智慧財產局員工消費合作社印製 圖26係顯示成爲作成圖25的半導體表面的各區域之罩 幕之閘電極1 8的形狀以及閘電極1 8與源電極接觸部24的配 置關係的俯視圖。 延伸於一方向的閘電極1 8係配置複數個。與實施例一 的圖4之不同點爲延伸於一方向的閘電極1 8的寬度其全體爲 相同的寬度。若加工精度充分地高的話，如此在閘電極1 8 的寬度內可形成聞極金屬接觸部26。 圖27係沿著圖25的Β-Β線的部分剖面圖。可看到接合 部分26中的閘電極18與閘極金屬電極27的連接的樣子。17爲 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 544932 A7 B7 五、發明説明（42) 閘極氧化膜、17a爲厚的場氧化膜，19爲源電極。若與實施 例一的圖5比較，得知無表面區域14。 (請先閱讀背面之注意事項再填寫本頁) 沿著此Β- Β線的的表面電極上的位置在圖3係以Β-Β線 表不。 而且，在本實施例九減少閘電極1 8的延伸於一方向的 終端部分的角，以不成爲銳角的形狀，惟即使以直角來終 端對本專利的內容的作用/功效也無影響。 [實施例十] 其次，圖28係顯示本發明第十實施形態之η通道縱型 MOSFET的閘電極18的形狀以及閘電極18與源電極接觸部24 的配置的俯視圖。令耐壓構造部與實施例——樣。 與實施例九的圖26所說明的構造的不同點爲除了在條 狀的閘電極1 8的兩端外，其中間也配設與閘極金屬電極的 接合部分2 6。 經濟部智慧財產局員工消費合作社印製 據此，對於內部閘電阻的降低以及接通電阻的增加抑 制具有效果。藉由在一半長度的條狀閘電極1 8的各個端配 設接合部分26，使實施例十的構造可提高主動部面積的效 率。 [實施例十一] 圖29係顯示本發明實施例十一之η通道縱型MOSFET 的耐壓支持層部分的斜視剖面圖。 到此爲止的例子電壓支持層都是單一的n_漂移層12° 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 4& 544932 A7 B7 五、發明説明（43 ) 但是，電壓支持層並非都必須是單一的層。 (請先閱讀背面之注意事項再填寫本頁) 近年來特別是在高耐壓的半導體裝置中，以在逆電壓 施加時空乏化的高雜質濃度，交互地排列寬度窄的η漂移 區域42a與ρ間隔區域42b的並聯ρη層作爲電壓支持層的所 謂超接合半導體裝置被開發。 圖30係本發明實施例十一之η通道縱型MOSFET的主 要部分的部分剖面圖。 在圖3 0中，在低電阻的η +汲極層11上交互地配置η漂 移區域42a與ρ間隔區域42b，此並聯ρη層42在逆電壓施加 時具有耐壓。例如各個寬度爲5 // m左右時，雜質濃度於單 一 rT漂移層12的100〜1000倍可高濃度化，而且厚度也可變薄 ，唯獨如此可降低接通電阻。 圖3 1 (a)係耐壓構造部分之半導體基板表面的俯視圖， (b)係沿著C-C線的剖面圖，（c)係沿著D-D線的剖面圖。 在圖31(b)p護環與η漂移區域42a與ρ間隔區域42b平 行，惟在圖3 l(c)p護環與η漂移區域42a與ρ間隔區域42b 直交。 經濟部智慧財產局員工消費合作社印製 在圖31(c)複數條ρ護環被ρ間隔區域42b短路，惟因ρ 間隔區域42b的厚度非常薄，由實驗確認在逆偏壓時因空乏 化故無問題。 如圖31(a)、（b)以及（c)可見的，n通道縱型MOSFET的 最外周部分阻止並聯ρη層42，當作高電阻區域38。 此外在圖30中，η漂移區域42a與ρ間隔區域42b的方 向與ρ井區域1 3的方向平行並非必定需要平行，直交也可 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（44 ) 以。直交的情形p井區域1 3因必定與η漂移區域42a與p間 隔區域42b接觸，故製造容易。 (請先閱讀背面之注意事項再填寫本頁) [實施例十二] 圖32係本發明實施例十二之η通道縱型MOSFET的耐 壓支持層部分的斜視剖面圖。 在低電阻的η +汲極層11上交互地配置η漂移區域42a與 P間隔區域42b的並聯pn42，更於其上形成n_漂移層12。 在其上側的η·漂移層12形成比p井區域13還上的構造 [實施例十三] 圖33係本發明實施例十三之η通道縱型MOSFET的耐 壓支持層部分的斜視剖面圖。可視爲實施例十一的MOSFET 的變形例。 經濟部智慧財產局員工消費合作社印製 即並聯pn層的p間隔區域42b被製作成球狀而不是薄 板狀而規則地配置，η漂移區域42a被製作成包圍p間隔區 域42b的區域。 藉由適當地選擇η漂移區域42a與p間隔區域42b的雜 質濃度，也能考慮這種構造。 [實施例十四] 圖34係本發明實施例十四之η通道縱型MOSFET的耐 壓支持層部分的斜視剖面圖。此實施例也可視爲實施例十 本紙張尺度適用中國國家標準（CNS ) A4規格（210><297公釐） 47- 544932 A7 B7_ 五、發明説明（45 ) 一的變形例。 (請先閲讀背面之注意事項再填寫本頁) 即並聯ρ η層的p間隔區域42b被製作成圓柱狀而不是 薄板狀而規則地配置，η漂移區域42a被製作成包圍p間隔 區域42b的區域。 圖35(a)係耐壓構造部分之半導體基板表面的俯視圖， (b)係沿著E-E線的剖面圖。 如圖35(a)以及（b)可見的，η通道縱型MOSFET的最外 周部分係當作高電阻區域38，而不是並聯ρη層42。 雖然根據以上幾個例子爲基礎而說明，惟主動部與耐 壓構造部係互相獨立，可自由地組合。而且，在任何實施 例中都令主動部的η·表面區域14爲η反摻雜區域34也可以 〇 特別是本發明的耐壓構造不限於具有MOS閘極的半導 體裝置，也能適用於平面電晶體（Planar transistor)等的雙載 子半導體裝置。 【發明的功效】 經濟部智慧財產局員工消費合作社印製 如以上的說明本發明顯示在MOS半導體裝置中，第一 導電型電壓支持層的表面露出部之第一導電型表面區域被 第二導電型井區域包圍，對包含第一導電型源極區域的第 二導電型井區域的表面積，藉由令其表面積的比爲0.01〜0.2 的範圍內，或令其形狀爲其寬度爲〇. 1〜2 // m的條狀，可大 幅地改善接通電阻與耐壓的取捨關係，可實現高耐壓同時 接通電阻低，再者開關損失也少的半導體裝置。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 544932 A7 B7 五、發明説明（46 ) 而且關於耐壓構造部，藉由依照耐壓使許多護環相互 接近而配設，可容易地實現平面接合的情形的理論耐壓的 97%以上。而且，藉由耐壓的提高，可使用薄的Si基板， 明顯地也與接通電阻的降低有關。 無須改變習知的MOS半導體裝置的工程等，僅變更圖 案使大幅的特性改善爲可能的本發明係特別在功率半導體 領域做出大的貢獻。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 4&In this embodiment, since the area ratio of the surface drain region is reduced, the JFET resistance increases. Therefore, the effect of reducing the on-resistance caused by reverse doping is large. Fig. 19 is a partial cross-sectional view of the withstand voltage structure portion of the n-channel vertical MOSFET according to the fourth embodiment. The difference from FIG. 13 of the vertical MOSFET of the first embodiment is that the withstand voltage Vbr = 600V, and the number of guard rings is six. This number is the same as 1.0xVbr / 100 = 6 obtained from the above formula which specifies the number η of the retaining rings. With this setting, the withstand voltage of 92% of 622V and the theoretical withstand voltage of 684V can be ensured. Of course, the number of retaining rings does not increase, and the pressure resistance can be higher. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the MOSFET of this fourth embodiment, replacing the n + drain layer with the p + drain layer or by configuring the low resistivity portion 12b and the p + drain layer of FIG. 42, as implemented. Examples 2 and 3 can be used as IGBT. The same applies to the example of the MOSFET up to the fourteenth embodiment, and the n + drain layer can be used as an IGBT. [Embodiment 5] FIG. 20 is a partial cross-sectional view of a withstand voltage structure portion of an n-channel vertical MOSFET according to a fifth embodiment of the present invention. The difference from Figure 13 of the vertical MOSFET of the first embodiment is the 4Θ of the guard ring. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 Α7 B7 5. The description of the invention (38) is Six, and a field electrode 35 of a polycrystalline silicon film forming a conductor on the field oxide film 17a between the two P-rings. (Please read the precautions on the back before filling this page.) In the actual use of the device, a voltage is applied between the drain electrode 20 and the source electrode 19. Items that are affected by reliability when subjected to long-term voltage application are charge storage effects on the device surface. If a voltage is also applied between the electrodes at both ends of the withstand voltage structure portion, the surface charge in the withstand voltage structure portion is induced, and the intervening insulating layer affects the semiconductor surface, especially the surface portion of the drift layer 12, disturbing the electric field inside the semiconductor and Related to pressure deterioration. In this example, since the field oxide film 17 on the surface of the interlayer insulating film 22 and the drift layer 12 of the withstand voltage structure portion is provided with a field electrode 35 of a polycrystalline silicon film, the electrostatic shielding effect can be used to suppress the surface charge. influences. In addition, the source electrode 19 and the gate electrode 18 cover the surface of the drift layer in the active portion, so that the structure is not affected by surface charges. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Between the n-surface area 14 between the guard rings and the intervening field oxide film 17a, a field electrode 35 of a polycrystalline silicon film with a conductive body is arranged to prevent the surface charge storage effect and to expect an effect on reliability. The withstand voltage is substantially the same as that of the second embodiment. In addition, the potential of the field electrode 35 is allowed to float, but a potential can be provided to give an appropriate potential. [Embodiment 6] FIG. 21 is a diagram showing a relative arrangement relationship between a source electrode contact portion 24 and a gate electrode 18 of an n-channel vertical MOSFET according to a sixth embodiment of the present invention. Let the pressure-resistant structural part be the same as the embodiment. The difference from the structure illustrated in FIG. 4 of the first embodiment is that in addition to the application of the Chinese National Standard (CNS) A4 specification (210 × 297 mm) on the strip paper size 44 544932 A7 B7 V. Description of the invention (39) (please first After reading the notes on the back side and filling out this page), both ends of the scent electrode 18 are provided with a sintered metal electrode joint portion 26 in the middle. According to this, it is effective in reducing the internal gate resistance and suppressing the increase in the on resistance. By arranging the joint portions 26 at each end of the half-length strip-shaped gate electrode 18, the structure of the sixth embodiment can improve the efficiency of the area of the active portion. The top view of the surface of the semiconductor substrate was interrupted during the n_surface region 14 on the way, and the small n_surface region was pinched. If the machining accuracy is high, this small n_surface area can be eliminated. In this sixth embodiment, the joint portion 26 with the gate metal electrode is provided with only one position in the middle of the gate electrode 18, but of course, a plurality of positions can also be provided with the gate electrode extending in the same direction. Seventh Embodiment FIG. 22 is a plan view showing a semiconductor substrate of an n-channel vertical MOSFET according to a seventh embodiment of the present invention. In addition, Fig. 22 and Fig. 2 are shown without the pressure-resistant structure. Let the pressure-resistant structure part be the same as the embodiment. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Directional shapes. The difference from FIG. 2 is that the surface area 14 extends in one direction and has a plurality of convex portions 31 in a direction that is substantially perpendicular to the extending direction. The arrangement frequency of the convex portions 31 is set to approximately every 250 // m, and the dimension of the extending direction and the vertical direction of the surface area 14 of the convex portion 31 is approximately 0.5 // m. Fig. 23 shows the masks of the regions that make up the semiconductor surface of Fig. 22. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 Α7 B7 V. Description of the invention (4〇) Gate electrode 1 8 And a plan view of the relative arrangement relationship between the gate electrode 18 and the source electrode contact portion 24. (Please read the precautions on the back before filling in this page) The difference between the shape in Figure 23 and the shape in Figure 4 is the gate electrode 18 extending in one direction, and the bridge with the gate electrode vertically arranged in the extending direction. (Bridge) 32. The frequency of the gate electrode bridge 32 is set to approximately every 250 // m, and the width of the gate electrode bridge 32 is set to 2.5 // m. If impurities are introduced by using the gate electrode 18 as a mask to form the p-well region 13, the lateral diffusion of the surface of the p-well region 13 is designed as 2 // m, and the bridge electrode 32 is below the gate electrode 32. It is connected to the diffusion regions from both sides of the bridge 32, so it becomes a P-well region 13. However, since the portion under the root of the bridge 32 is not connected to the diffusion regions from both sides, the convex portion 31 of the n-surface region remains. In this example, since the gate electrode 18 is connected by the bridge 32, the gate resistance is reduced and the on-resistance is also reduced. [Embodiment 8] Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 24 shows the gate electrode 18 of the n-channel vertical MOSFET according to the eighth embodiment of the present invention, and the relative arrangement relationship between the gate electrode 18 and the source electrode contact portion 24 Top view. The pressure-resistant structure portion is the same as in the first embodiment. The difference from the structure illustrated in Fig. 23 of the seventh embodiment is that, in addition to the two ends of the strip-shaped gate electrode 18, a junction portion 26 with a gate metal electrode is also provided in the middle. According to this, it is effective in reducing the internal gate resistance and suppressing the increase in the on resistance. By arranging the joint portions 26 at each end of the half-length strip-shaped gate electrode 18, the structure of the eighth embodiment can improve the efficiency of the area of the active portion. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 male). (Centi) 4 ^ 544932 Α7 Β7 5. Description of the invention (41) rate. (Please read the precautions on the back before filling in this page.) The top view of the surface of the semiconductor substrate is interrupted on the way. The surface area 14 is interrupted, and the small surface area is sandwiched. If the machining accuracy is high, this rT surface area can be eliminated for 14 days. The junction part with this gate metal electrode is in this eighth embodiment. Of course, although only one position is arranged in the middle of the gate electrode extending in one direction, the same structure can also be used to configure a plurality of gate electrodes extending in one direction. Locations. Ninth Embodiment FIG. 25 is a plan view showing the surface of a semiconductor substrate of an n-channel vertical MOSFET according to a ninth embodiment of the present invention. In Fig. 25 and the embodiment, a pressure-resistant structure portion is omitted and shown. Let the pressure-resistant structure part be the same as the embodiment. In FIG. 25, the η_surface region 14 is a stripe extending in one direction, and a plurality of (the dots are omitted and shown in plural) are arranged in parallel and surrounded by a P-well region 13. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. FIG. 26 is a plan view showing the shape of the gate electrode 18 and the arrangement relationship between the gate electrode 18 and the source electrode contact portion 24 as the masks of the regions on the semiconductor surface of FIG. 25. . A plurality of gate electrodes 18 extending in one direction are arranged. The difference from FIG. 4 of the first embodiment is that the width of the gate electrode 18 extending in one direction is the same as a whole. If the machining accuracy is sufficiently high, the metal electrode contact portion 26 can be formed within the width of the gate electrode 18 in this way. Fig. 27 is a partial cross-sectional view taken along the line B-B in Fig. 25. The connection between the gate electrode 18 and the gate metal electrode 27 in the joint portion 26 can be seen. 17 is the size of this paper. It is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 544932 A7 B7. 5. Description of the invention (42) The gate oxide film, 17a is a thick field oxide film, and 19 is the source electrode. Compared with FIG. 5 of the first embodiment, it is found that there is no surface area 14. (Please read the precautions on the back before filling out this page.) The position of the surface electrode along this Β-Β line is indicated by the Β-Β line in Figure 3. Further, in the ninth embodiment, the angle of the terminal portion of the gate electrode 18 extending in one direction is reduced so as not to become an acute angle, but the effect / effect of the contents of this patent is not affected even if the terminal is terminated at a right angle. [Tenth Embodiment] Next, FIG. 28 is a plan view showing the shape of the gate electrode 18 and the arrangement of the gate electrode 18 and the source electrode contact portion 24 of the n-channel vertical MOSFET according to the tenth embodiment of the present invention. Let the pressure-resistant structure part be the same as the embodiment. The difference from the structure illustrated in Fig. 26 of the ninth embodiment is that, in addition to the two ends of the strip-shaped gate electrode 18, a junction portion 26 with the gate metal electrode is also provided in the middle. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This has the effect of reducing the internal gate resistance and suppressing the increase of the on-resistance. By arranging the joint portions 26 at each end of the strip-shaped gate electrode 18 of half length, the structure of the tenth embodiment can improve the efficiency of the area of the active portion. [Embodiment 11] FIG. 29 is a perspective sectional view showing a portion of a withstand voltage supporting layer of an n-channel vertical MOSFET according to Embodiment 11 of the present invention. The examples so far have a single n_drift layer of 12 °. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 4 & 544932 A7 B7 V. Description of the invention (43) However, The voltage support layers do not all have to be a single layer. (Please read the precautions on the back before filling this page.) In recent years, especially in high-withstand voltage semiconductor devices, the narrow η drift regions 42a and A so-called super-junction semiconductor device having a parallel ρη layer in the ρ space region 42b as a voltage support layer has been developed. Fig. 30 is a partial cross-sectional view of a main part of an n-channel vertical MOSFET according to the eleventh embodiment of the present invention. In FIG. 30, the η drift region 42a and the ρ spacer region 42b are alternately arranged on the η + drain layer 11 having a low resistance. This parallel ρη layer 42 has a withstand voltage when a reverse voltage is applied. For example, when each width is about 5 // m, the impurity concentration can be increased to 100-1000 times that of a single rT drift layer 12, and the thickness can be made thinner. This alone can reduce the on-resistance. Fig. 31 (a) is a plan view of the surface of the semiconductor substrate of the withstand voltage structure part, (b) is a cross-sectional view taken along the line C-C, and (c) is a cross-sectional view taken along the line D-D. In Fig. 31 (b), the p-ring and the n-drift region 42a are parallel to the p-spaced region 42b, but in Fig. 3 (c) the p-ring and the n-drift region 42a and the p-spaced region 42b are orthogonal to each other. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a number of ρ guard rings in Figure 31 (c) that were short-circuited by the ρ spacer region 42b. However, due to the very thin thickness of the ρ spacer region 42b, it was confirmed by experiments that the space was depleted during reverse bias So no problem. As can be seen in Figs. 31 (a), (b), and (c), the outermost portion of the n-channel vertical MOSFET prevents the pn layer 42 from being connected in parallel as a high-resistance region 38. In addition, in FIG. 30, the direction of the η drift region 42a and the ρ interval region 42b is not necessarily parallel to the direction of the ρ well region 13. Orthogonality may also apply the Chinese National Standard (CNS) A4 specification (210X297 mm) on this paper scale. ) 544932 A7 B7 5. Description of the invention (44). In the case of orthogonal intersection, since the p-well region 13 is necessarily in contact with the n-drift region 42a and the p-interval region 42b, manufacturing is easy. (Please read the precautions on the back before filling this page) [Twelfth Embodiment] Fig. 32 is an oblique cross-sectional view of a voltage-supporting support portion of an n-channel vertical MOSFET according to the twelfth embodiment of the present invention. On the low-resistance n + drain layer 11, a parallel pn42 of an n-drift region 42a and a P-spaced region 42b is alternately arranged, and an n_drift layer 12 is formed thereon. An upper structure of the η · drift layer 12 is formed on the upper side than the p-well region 13 [Embodiment 13] FIG. 33 is an oblique cross-sectional view of a withstand voltage supporting layer portion of an η-channel vertical MOSFET according to Embodiment 13 of the present invention . This can be regarded as a modified example of the MOSFET of the eleventh embodiment. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. That is, the p-spaced regions 42b of the parallel pn layer are made in a spherical shape instead of a thin plate and are regularly arranged. The n-drift region 42a is made of a region surrounding the p-spaced region 42b. This structure can also be considered by appropriately selecting the impurity concentrations of the n-drift region 42a and the p-interval region 42b. [Embodiment 14] FIG. 34 is a perspective cross-sectional view of a withstand voltage supporting layer portion of an n-channel vertical MOSFET according to Embodiment 14 of the present invention. This embodiment can also be regarded as the tenth embodiment of the present invention. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 > < 297 mm) 47- 544932 A7 B7_ V. Variation of the first description of the invention (45). (Please read the precautions on the back before filling this page) That is, the p-spaced regions 42b in parallel ρ η layers are made into a cylindrical shape instead of a thin plate and arranged regularly. The η drift region 42a is made to surround the p-spaced region 42b. region. FIG. 35 (a) is a plan view of the surface of a semiconductor substrate of a withstand voltage structure portion, and (b) is a cross-sectional view taken along line E-E. As can be seen in Figs. 35 (a) and (b), the outermost portion of the n-channel vertical MOSFET is treated as a high-resistance region 38, rather than a parallel pn layer 42. Although explained based on the above examples, the active part and the pressure-resistant structure part are independent of each other and can be freely combined. Furthermore, in any embodiment, the n-surface region 14 of the active portion may be the n-doped region 34. In particular, the withstand voltage structure of the present invention is not limited to a semiconductor device having a MOS gate, and can be applied to a flat A bipolar semiconductor device such as a transistor. [Effect of the invention] Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as described above. The present invention shows that in the MOS semiconductor device, the first conductive type surface area of the surface exposed portion of the first conductive type voltage support layer is second conductive. 1 type well area surrounded, the surface area of the second conductive type well region including the first conductive type source region, by making the ratio of its surface area within the range of 0.01 ~ 0.2, or making its shape to have a width of 0.1 The strip shape of ~ 2 // m can greatly improve the trade-off relationship between the on-resistance and withstand voltage, and can realize a semiconductor device with high withstand voltage and low on-resistance, and less switching loss. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 544932 A7 B7 V. Description of the invention (46) Moreover, regarding the pressure-resistant structure part, many guard rings are arranged close to each other according to the pressure resistance, and can be configured. At least 97% of the theoretical withstand voltage in the case of easily achieving planar bonding. Furthermore, by increasing the withstand voltage, a thin Si substrate can be used, which is obviously related to a reduction in the on-resistance. It is not necessary to change the engineering and the like of the conventional MOS semiconductor device, and it is only possible to change the pattern to make a large-scale characteristic improvement possible. The present invention makes a great contribution especially in the field of power semiconductors. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm) 4 &
