TW553891B - MEMS and method of manufacturing - Google Patents

Abstract

The present invention relates to micro electro-mechanical systems (MEMS) and production methods thereof, and more particularly to vertically integrated MEMS systems. Manufacturing of MEMS and vertically integrated MEMS is facilitated by forming, preferably on a wafer level, plural MEMS on a MEMS layer selectively bonded to a substrate, and removing the MEMS layer intact.

Description

553891 发明 Description of the invention (The description of the invention should state: the technical field, the prior art, the content, the embodiments, and the simple description of the invention) MEMS) and its manufacturing methods, and 5 and more specifically, about vertically integrated micro-electro-mechanical systems. [Prior Art 3 Background of the Invention The field of micro-electro-mechanical systems has entered a rapid growth period due to the explosion of MEMS sensor applications. When the attention of the mass media is focused on genomic experiments and micro-robots on strong 10-tone chips, the biggest advantage of MEMS technology may not come from making tools and sensors smaller, but rather making them cheaper. Most MEMS devices are still independent components. The advantages of this approach to the ubiquitous integration costs will be lost. The MEMS device is conventionally manufactured using a method 15 suitable for the manufacture of electronic microchips. Integration can revolutionize microelectronics. Large-scale integrated circuits (LSIs) place millions of transistors on a single chip, while continuing to have greater capabilities in the market to steadily reduce costs. Microelectronics has moved to the next level to integration, manufacturing a system on a wafer or manufacturing several systems in a package. The integration of MEMS devices on a single chip still remains more than 20 undetected. Those challenges of MEMS integration are very different from those of CMOS (Complementary Metal Oxide Semiconductor). While the CMOS technology has reached the milestone of 100 million transistors, the world of microcomputer electrical systems is still largely composed of individual devices. The MEMS industry is very fragmented, with very little integration. Due to the traditional micro-electromechanical system 5 553891 ^ 说明, the description of the invention, the high requirements of the system manufacturing process, most micro-electro-mechanical systems are separate devices. The integration of MEMS devices, in addition to reducing manufacturing costs, will greatly expand the capabilities of these devices. As the geometry shrinks, the sensitivity of most microsensors decreases. For example, the output of a torsional capacitive accelerometer decreases by 1 to the fifth power of the lateral dimension. Problems with line capacitance and signal-to-noise ratio make sensors without circuits on the substrate useless for shrink detection and signal reduction procedures. In industry today, the main focus of MEMS sensor integration is to provide a control circuit on a chip. The automotive industry has led the way in combining different sensors on a single chip. For example, many pressure sensors and accelerometers meet the temperature sensitivity of the response curve by adding a thermometer on the chip for temperature compensation. Further measures have been completed. For example, Toyota Nippondenso has reported a car sensor kit that combines sensors for engine pressure and temperature 15 on the same chip as a trigger for an impact airbag2. However, the sensor kit is still a niche in very special-function markets and mass production, because building a kit requires complex designs and huge resources. Integration remains a difficult issue. Polycrystalline silicon is a core material for micromachining, and an inconsistent example of MEMS integration. The high temperatures of deposition (approximately 630 ° C) and annealing (> 900 ° C) are incompatible with aluminum and copper metallization. This process must be compromised or required.

Gabrielson, TB "Basic Noise Limits for Minimizing Sound and Vibration Sensors", ASME Journal, Journal of Vibration and Acoustics, Vol. 17 (4), p. 405 (1995) . 2 T. Fujii, Y. Gotoh, and S. Kuroyanagi, "Manufacture of micro-membrane pressure sensors by micromachining", Sensors and Actuators, Vol. A34, p. 217 (1992 year). 553891 玖, description of the invention More expensive, more resistant, refractory metals such as tungsten 3 must be used. The annealing of micro-electro-mechanical systems for temperature-sensitive film materials, very deep etching, anode bonding, and the required strain relief makes integration a unique series of problems. Designing an integrated sensor kit on a single chip can cause many difficult tasks in combination with a conventional accelerometer with, for example, a 1C temperature sensor or a thin film thermal resistor. And the resulting design will not be changed. Upgrading to an improved sensor requires a complete redesign and purchase of a new photomask set. Vertical integration or stacking MEMS in the same package is a compelling method to reduce package size, increase circuit density, save substrate space, and improve efficiency and functionality. Both the "delay and the reduction of power secrets are spearheads for stack integration. #If these are thin and stacked on top of each other, the advantages in cost and circuit density may be very large. For the product In terms of bulk circuits and MEMS programs, the third 15th dimension of the silicon wafer still retains a large amount of unused space. At present, the commercialization method of vertical stacked 2D devices is usually wafer scale and relies on wafer grinding to thin. Most methods rely on through-hole or wire bonding, stacking mother and child wafers to connect to each other. At present, all methods have restrictions on package size, cost, reliability, and yield impact. Despite these 20 difficult 'stacking devices to achieve Three-dimensional integration can be seen in its application, especially = 疋 in the combination of micro-electromechanical systems and ASIC (application characteristic integrated circuit) controller. High-density memory packages made by stacking individual chips have been integrated micro-buttons The surface micro-mechanical guarding technology, PhD dissertation, Stanford University 553891 玖, the invention description has special applications. Irvine, California (Irvine) Sensor company (Irvine sensors) and International Business Machines Corporation (IBM) have begun a three-dimensional package. The separated dies have been stacked 5 and connected to each other using the edge lift-off process 4. Known good The grains (Known-good-die (KGD)) are thinned. Soft solder bumps at the edges of the grains are used to arrange and interconnect the stacked grains. The grains are placed in an epoxy Resin substrate. The epoxy resin helps to arrange the grains of different sizes and is used as the surface of the interconnection. With the demand of KGD, the individual stacking and interconnection of the wafer will make this a very Expensive manufacturing method. Cubic Memory has already begun another 3D package. The company uses gold interconnect patterns over polyimide insulation layers deposited on the entire wafer. Manufacture of high-density, stacked memory modules. However, stacking and vertical interconnects are still another chip scale. 15 San Jose, California, Tessera, along with Intel, have already begun another 3-dimensional package Line, bonded via a micro ball grid array, the wafer is attached to a flexible substrate, and the wafer ribbon with its duty to do Z-folded, and the development of a wafer-scale package stack.

Ziptronix is clearly a wafer-scale stack for developing integrated circuits. For 20 straightening, stress management, thermal management, high-density interconnects, and productivity, considerable work remains to be done. Available vertical integrations have various drawbacks. A major flaw J. Minahan, A. Pepe, R. Some, and M. Suer, "Short form of 3D stacking (memory chip package)," Proceedings of the 42nd Electronic Components and Technology Conference, San Diego, California Brother (1992). 553891 玖, description of invention 疋 due to yield loss. All device stacking methods currently in use on the market are at the grain scale. Individual dies are prepared, arranged, stacked and connected. The processing is expensive, and the yield loss of the stack is the composite yield loss of each device in the layer. Increased yield loss is sometimes tolerable for cheap devices 5 such as static random access memory (SRAM) stacks. But when more expensive devices are being stacked, the solution is to use a known good die (KGD). For KGD, each unpackaged die is burned and tested. In addition, the stack needs to be tested electronically after each layer is completed. This method is very expensive and these applications have been limited to advanced users, such as military and satellite technology. Another disadvantage of traditional vertical integration is that the technology is limited to the grain size. With the exception of Ziptronix's sooner-to-reaeh_the market approach, all stacked device approaches are at the die scale. These technologies represent a significant economic advantage for wafer-scale manufacturing. The high cost of processing and testing individual grains limits the application of these methods to higher orders. Another disadvantage of traditional vertical integration is related to material incompatibility. Organic adhesives and potting compounds were used to build the stack. The use of adhesives and casting compounds is incompatible with many useful methods. The thermal expansion coefficient (TCE) of this adhesive usually does not match the TCE of the wafer. During the subsequent 20 treatments and during plant operation, temperature and thermal cycling must be severely restricted to avoid grain bursting and delamination. And most of the adhesives are organic compounds and are therefore incompatible with semiconductor processes that include oxidizing environments, high temperatures, and exposure to aggressive chemicals. Current sensor integration is still a very expensive and design intensive effort. 9 发明 Description of the invention The integration of sensors is mainly based on automobiles, and the high design cost is shared among a very large number of parts. It requires new integrated systems and methods, so that integrated MEMS devices have huge potential in a wider range of applications. Semiconductor and MEMS devices are fabricated on a small portion of the thickness of the wafer '. During the manufacturing period, most of the wafer thickness is used for structural support. Indeed, back-grinding—the final stage of the wafer before packaging—improves thermal transfer. Another feature of very thin devices is that they are flexible, which is advantageous in managing the mechanical stress of wire bonding and packaging. Although very thin layers have advantages, thinning to less than 100 microns is very responsible, so it is rarely done. To avoid impacts penetrating any area of the wafer, grinding must be performed at a low rate and careful wafer thickness positioning must be performed repeatedly. Thin wafers with similar complexity, thickness uniformity, and penetration can be completed by wet back etching or plasma etching on the back. One layer can be incorporated into the wafer as a finish or finish layer. For example, a nitrided layer can be incorporated into silicon as a hard polishing stop layer, or a boron implanted layer can stop selective dopant etching. When these methods work, they are expensive and difficult to implement. The use of electromechanical system sensors has grown rapidly. For all types of microsystems, the market size in 2000 was estimated to be more than $ 14 billion, and the CAGR was estimated to be 21%. Environmental monitors are less than 5% in this market, but are expected to have a CAGR of 35% over the next four years, which is much higher than the market average of 5. Improved cost and reliability caused Xu RH · Grace, "New MEMS and its fascinating applications", Sensor Magazine, July 2000. 553891 玖, Invention Description Many traditional sensors were replaced with The main driving force of microinductors. Microinductors are effective for measuring acceleration, vibration, pressure, temperature, humidity, strain, proximity effects, rotation, sound emission and many other things. Examples of applications include automotive airbag safety systems , Other automotive applications, safety systems, vibration sensors, biomedical applications. Automotive airbag safety systems are triggered by MEMS accelerometers. With MEMS sensors, the airbag system is saved every year. More than 1,000 people. The National Highway Traffic Safety Administration (NHTSA) estimates that the smart airbag system has a sensor array that can adjust the intensity and position of the impact, and adjust the passenger's appearance, position, movement and weight. Hundreds of lives are saved each year.6 The sensor market for airbag deployment has enjoyed the first 5 years There is a rapid growth of CAGR over 20-25%. There are many micro-electro-mechanical systems in automotive applications. Micro-electro-mechanical system sensors measure 15 miles of oil, fuel, refrigerant, transmission and brake oil levels. Pressure sensors detect anti-brake Lock-up (ABS) line pressure, vacuum level, fuel injection pressure, tire pressure and more. Chemical and flow sensors are used to detect exhaust components, inlet flow. Temperature sensors optimize engine performance, And together with the humidity sensor can determine the cockpit comfort. The vehicle's power control for determining the 20 sideslip rate and the driving safety and convenience are improved by avoiding impact proximity sensors. There are many more. Cheaper and There are many more powerful sensor kits that can increase driving safety and improve seat inspections. "Advanced Airbags, Final Economic Evaluation", FMVSS No. 208, NHTSA Regulation Analysis & Evaluation, Planning and Policy Office, 2000 May. 11 553891 玖, description of the invention The potential for comfort and making the engine last longer and be friendlier to the environment. The security system combined with the sensor type can expand the detection network and limit the false alarms through intelligent redundancy of alarms. Proximity, motion, vibration, and thermal measurement are combined. The integrated sensor array has a huge potential in monitoring battle forces and mobile battlefield sensor networks. The integration of miniaturized wireless communications with micro-sensor kits can give smart sensor networks a huge potential7. The vibration sensor protects the disk drive by prohibiting read / write operations during mechanical interference. Data from vibration sensors can extend product life, 10 and predict imminent damage to critical components, reducing downtime for critical mission systems. Environmental monitors hold great promise for product inventory and quality control, as well as water and air testing. The application of biomedicine is truly an innovation and goes far beyond DNA sequencing. It includes new drug discovery technologies and new and rapid disease tests. Improvements in drug release methods, such as biomechanical devices such as hearing aids and artificial vision, have dramatically improved the quality of life. Optical converters and optical conversion components (for example, variable optical attenuators) have also been proposed and formed using micro-electro-mechanical systems, such as' including rotating to direct light in the direction needed, imparting delay and other functions. Microscope of sex. The market for this microsystem is large and is getting larger at a rapid rate. A Cost-Effective and Popular Any One Can Generate Many New, Much, M. Kahn, RH Katz, and KSJ Pister, "Mobile Networks for Smart Dust", Service ... , ACM Intership Conference, Sea State, Washington, 2nd Annual Move ^ 12 553891 发明, invented a method to excite the application of a sensor kit with huge potential. Cheaper and more powerful sensors have a huge positive impact on every aspect of society.

Various sensor technologies for MEMS temperature and humidity and vibration sensors already exist. Temperature can be measured by many tools. The most common are resistance temperature detectors (RTDs), thermal resistors, and integrated circuit devices. It is also possible to use capacitance measurements of pressure changes to generate an electrical signal based on temperature changes. This is usually done as a pressure sensitive oscillator, which makes the power requirements quite high. RTDs also require a relatively high operating current, and self-heating may make shortening the duty cycle difficult. On the other hand, a thin-film thermal resistor driven by a very low power was directly constructed. An amorphous germanium thermal resistor has been reported to consume only 1 microampere 8 at 2 volts. The temperature coefficient of the resistor is reported to be approximately -2% / K at room temperature. With such a low current consumption, the self-heating effect of the thermal resistor can be safely ignored. Another advantage is that the sensor can operate from a power supply (battery) without the need for an external current source. The response curve, although parabolic, has sufficient linearity and may not require linearization. The integrated circuit inductor derives the temperature from the temperature dependence of the forward voltage of the silicon junctions. Commercial products are available for complementary metal-oxide-semiconductor (CMOS) thermometers operating at 3 volts 20. Low supply current, well below 50 microamps, produces very low self-heating-less than 0.1 ° C. National Semiconductor offers a low-power-driven G. Urban, A. Jachimowicz, H. Ernst, S. Seifert, J. Freund »F. Kohl," Ultra-sensitive Flow Sensors for Liquids Using Thermal Microsystems "European Sensors ( Eurosensors) XIII, The 13th European Conference on Solid State Converters, p. 691 (1999). 13 发明 Description of the invention A CMOS thermometer which operates at 3 volts < 10 microamperes (National Semiconductor Part Number LM19). The cost of the quantity < 1000 is $ 0.20. Analog Devices manufactures a CMOS thermometer with a built-in shutdown function that reduces the supply current to less than 0.5 micron1. The relative humidity sensor detects the response to changes in material properties by absorbing atmospheric moisture. The material properties of interest may be, for example, the dielectric function in a capacitance gauge, the electrical impedance or thermal conductivity of a resistive humidity sensor. Capacitive relative humidity (RH) sensors are a simple device used in many industrial and surveying applications. The capacitive RH sensor has a low temperature coefficient and low power consumption (< 10 microamperes). Standard MEMS vibration sensors are based on measurements of capacitance, piezoresistance, and piezo. An external power source is required for various capacitive sensors or bridge piezoresistive devices. However, piezoelectric (PE) produces a power signal that does not have a drawing current from an external σ 源 power source. The impedance output signal comes from a piezoelectric sensor, making predicate measurements susceptible to electromagnetic noise. Influence, and need to be raised in the measurement circuit. Many sensors also have electricity attached to the board, such as batteries. Generally available batteries, lithium primary batteries have been used to meet long-term battery life. Lithium batteries have an operating voltage of 3 volts, high energy density, long (> 10 years) shelf life, good low temperature operation, and excellent leak resistance. They are also suitable for pulsed discharges, which should have the duty cycle required by the inductor kit. Long battery life requires a low average current consumption. Low average current consumption can be achieved by a very low constant current consumption on an always-on device or 1 part number TM Gang TMP36 / TMP37 American Analog Component Corporation, Zhuwood, Mass. (N '"). 14 553891 发明, description of the invention is accomplished by using a very low power clock relay to increase the duty cycle of the inductor kit to a higher operating current. Commercial lithium coin batteries have an energy density of 25-1700 milliamp hours (mAh), and most types of lithium batteries have a capacity of 300-400 mAh. 5 Consider a 40 mAh battery (Tadiran TL-5186). In order to achieve ten-year battery life, the average current consumption must be less than 4.5 microamperes. This is a very low operating current and is outside the requirements of an available accelerometer (vibration sensor). A larger or more expensive cylindrical battery must be used (useful up to 19 amp-hours), or the sensing kit must be triggered or cycled for 10 loads. When the temperature and humidity are suitable for slowly changing variables that are slow to sample once per hour or slower, a random event is hit. The vibration sensor must always be on, or it must be able to start quickly after a starting impulse. Encapsulation shock is a fairly short-term event (0 milliseconds), so the trigger shock sensor must be able to respond in the next 15 milliseconds in sleep mode. The Dallas Semiconductor DS1306E is a real-time clock with alarms and operates at an average power consumption of 1 microwatt to ensure that the total sleep power dissipation is 1 microwatt. A room temperature drainage curve shows that if the outflow current is < 30 milliamps, a ten-year operating life for a 3 volt battery is 20 possible 1G. Operation in very cold conditions (_21 ° C) will reduce life by about an order of magnitude. In order to adapt to the large-scale use of the MEMS system mentioned at the same time, and integrate MEMS into more aspects of daily life, therefore, it has been more http://data.energizer.com/datasheets/_part of / splash htm 15 553891 发明, the manufacturing method of the invention is needed. It is impossible to manufacture MEMS based on wafer-scale technology or wafer-scale technology using traditional thinning technology for economic MEMS integration. OBJECT OF THE INVENTION 5 Therefore, a main object of the present invention is to provide a low-cost micro-electro-mechanical system. Another object of the present invention is to provide a vertically integrated micro-electro-mechanical system. Still another object of the present invention is to provide a device including one or more micro-electromechanical systems and a combination of electronics, optical systems, photovoltaics, photovoltaics, thermal management (thermal post-calling, howling) And / or other functionally vertically integrated micro-electro-mechanical systems. Another object of the present invention is to provide a method for manufacturing a micro-electro-mechanical system and a vertically-integrated micro-electro-mechanical system. In the electronic and / or other structural processing conditions, a device layer is provided on a support layer. Another object of the present invention is to provide a method for manufacturing a micro-electromechanical system and a vertically integrated micro-electro-mechanical system, which are usually included in a Among the conditions that allow MEMS, microelectronics, and / or other structural processing, a device layer is provided on a support layer, so that the device layer with the Removal (for example, being peeled off) without knowing that σ 4 has minimal damage to the structures formed on the device layer, whereby the device layer may form Many device layers that form a micro-electro-mechanical system, or different or similar useful structures can be arranged and stacked to form a vertically integrated micro-electro-mechanical system kit. Description of the invention Summary of the invention Several methods and devices. The problems and disadvantages discussed above and other prior art techniques can be overcome or reduced. At the same time, these objectives of the invention can be achieved. Thin-scale wafer layer removal, transfer and stacking provide a 3D integration of electromechanical systems is an effective and efficient system. Wafer bonding and debonding is used to make a custom wafer that enables 3D integration of the device economically. 10 MEMS devices or device kits are Manufactured using a multi-layer substrate that includes a first layer that is selectively attached or bonded to a second layer. This layer is more a layer than a wafer. This method uses a layer that is designed to allow thin `` useful, '' layers It can be removed and transferred without damaging the wafer starting substrate of the device being processed on the useful layer. This technique can be used to simplify simultaneous Enabling design and processing, 15 and vertical integration of sensors and controllers at wafer scale. Selective bonding technology can be used to design directly using simplified thin layer transfer. In this way, any MEMS sensor Cheap and flexible integration with actuators and hybrid MEMS and microelectronics can be achieved. The technology can be extended to produce very high density microelectronics. This selective bonding method is provided by providing an effective cost tool This design method was opened to generate and transfer thin layers, in order to form a large number of fiuoleaf structures (MFT). The complex processing steps in the past can be divided into simple steps. The difficulties of notching and other traditional lifting techniques can be These component layers are stripped and replaced one at a time on a wafer scale. 17 553891 发明, description of the invention Therefore, using a 5㈣ layer of starting crystal ®, it can transfer any one layer. Among other things, the non-selective bonding method can be applied at the component level and further applied to the wafer scale transfer including the entire completed MEMS and microprocessing system, thereby effectively integrating the tape To MEMS 5 system technology. A method of manufacturing a micro-electro-mechanical system typically includes selectively adhering a first layer, optionally with structures on or in it, to a second floor, removing the first layer, using similar or dissimilar The procedure is repeated with no structure (or none at all) and the majority layers are stacked to form a 3 10-dimensional integrated structure. This method allows inexpensive microelectronics, microelectromechanical system sensors, microelectromechanical system actuators, hybrid microelectromechanical systems_microelectronics, or any combination thereof. The above-discussed and other features and advantages of the present invention are addressed by the following: See detailed descriptions and illustrations for detailed understanding and understanding of those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram illustrating an embodiment suitable for forming a layered structure of a micro-electro-mechanical system and other associated micro-devices; FIG. 2 is a description of an internal structure suitable for a micro-electro-mechanical system according to an embodiment A layer containing 20 objects; FIG. 3 illustrates a support layer according to an embodiment; FIG. 4 illustrates a layer of inclusions suitable for a micro-electromechanical system according to an embodiment; FIG. 5 illustrates a layer according to an embodiment Describe a support layer; 18 553891 发明 Description of the invention Figure 6 describes a layer of content suitable for a micro-electromechanical system according to an embodiment; Figure 7 describes a support layer according to an embodiment; Figure 8 is based on An embodiment describes a layer of content 5 suitable for a micro-electro-mechanical system; FIG. 9 illustrates a support layer according to an embodiment; FIG. 10 illustrates a content of a micro-electro-mechanical system according to an embodiment. Figure 11 depicts a support layer according to an embodiment; 10 Figure 12 depicts a layer of inclusions suitable for a micro-electro-mechanical system according to an embodiment; layer 13 depicts a support layer according to an embodiment ; For the 14th series One dimension of the joining geometry of the structure in Fig. 1 Fig. 15 depicts another aspect of the joining geometry of the structure in Fig. 1; Fig. 16 depicts the structure used in Fig. 1 Another aspect of the joining geometry; FIG. 17 is a description of an eight-blade selective step according to an embodiment; 20 FIG. 18 is an intermediate structure following the step according to an embodiment Figure 19 is the step of peeling off the structure in Figure 18; Figure 20 illustrates a separation step by using selective implantation through a mask structure according to a conventional example; 19 553891 发明, Figure 21 of the description of the invention An intermediate structure after this step is described according to an embodiment; FIG. 22 illustrates the steps of stripping the structure from FIG. 21; and FIG. 23 illustrates a method by using non-selective implantation according to an embodiment. Separation step; FIG. 24 illustrates an intermediate structure after the steps of FIG. 23 according to an embodiment; FIG. 25 illustrates the steps of stripping the structure from FIG. 24; Use selective planting around 10 points Fig. 27 illustrates an intermediate structure after the steps of Fig. 26 according to an embodiment; Fig. 28 illustrates the steps of peeling off the structure of Fig. 27; Fig. 29 shows an actuating micrograph to be recorded Side view and top view of a peeling layer of a mirror, actuator or other micro-electromechanical system; Figure 30 shows a side view and a top view of a peeling layer, such as a plurality of actuated micromirrors, actuators or MEMS processing on it; Figure 31 shows another peeling layer with multiple voids to record actuable micromirrors, actuators or other MEMS; 20 Figure 32 shows a logic device with multiple The peeling layer is operatively coupled to the combined MEMS device shown in FIG. 30; FIG. 33 shows the peeling layer of a plurality of memory devices to be operatively coupled to the MEMS devices shown in FIGS. 30 and 32, respectively. Combined MEMS device and logic device; 20 玖. Description of the invention Figure 34 shows a plurality of vertically integrated MEMS devices including a wafer-level combined logic and memory; and Figure 35 shows a Vertical integration of other MEMS devices. ί: Detailed description of the preferred embodiment 3 In the present invention, the MEMS device is stacked vertically, which provides other microsystems (including 'but not limited to microelectronics, microfluidics, thermal management, and the like) 3D integration. Compared with the situation of CMOS technology, the critical dimension of the microcomputer electrical system device is quite large, which greatly relaxes the wafer-scale alignment standard. For a given device, the number of pins required is a bit small. In contrast to integrating microelectronics vertically, vertical interconnections are simplified. For example, commercially available thermometer u and hygrometer 12 chips require only a single, twisted pair of wires for power and data communications. Vertical interconnections can be made large, which has a significant positive impact on reliability. Another advantage of the MEMS sensor stack is that the MEMS sensor stacking condition is relatively low power consumption and direct thermal management. By using this manufacturing method and using wafer-scale bonding, the cost of vertical integration is the same as the cost of forming a separate device, and it will ultimately be significantly less than the cost of forming a separate device. A vertically integrated micro-electro-mechanical system kit, including, for example, one or more sensors, optical switches or other functional micro-electro-mechanical systems is disclosed. The manufacturing method is flexible, so that any MEMS hybrid combination is l-wire ™ tt%:, DS182〇 (a ^ tt) 0

DanAwtrey, 1-Truncation Induction & , , , Sensor (sens〇r) H7 roll, 2〇〇〇, Year eight ^ c 21 553891 玖, Description of the invention It is easy to upgrade the design. This method will reduce the cost of integrating microcomputer electrical systems, And allows use in new application categories.  In general, The bond strength is controlled to produce a starting wafer that allows the entire device layer to be removed and transferred after completion. These bonded wafers are set up to withstand device processing, And still allow stripping of this thin device layer at the wafer scale, No difficult grinding and etching.  A new method for manufacturing SOI wafers, It is a transfer of a thin layer on a silicon wafer by controlling splitting along the plane of the ion implantation damage. Usually, this layer is permanently bonded to an oxidized silicon wafer, To form a silicon_10 oxide-silicon laminate. No adhesive was used for this joint. Through the entire wafer surface or in a selective pattern of strong and weak junctions, Controlling the strength of the joint is another way to form a permanent joint. for example, The joint month b can be controlled by nano-scale rough stitching. These wafers with energy-controlled internal planes can be used, Designed to manufacture reliable sensors. After manufacturing, Each thin sensor device layer is transferred to a handle wafer. The transfer and bonding of this device layer occurs at the wafer scale, That is, The entire top layer is transferred layer by layer, And directly bonded to the pull wafer. Additional layers of sensors or controllers can be stacked on the pull wafer, Overlay the original transfer layer to produce a 3-dimensional sensor kit. This method allows any type of sensor to be integrated into a stacked kit.  Referring to Figure 1, A selectively bonded majority of the substrate 100 is shown. The multi-layer substrate 100 includes a layer 1 having an exposed surface 1B and a surface 1A selectively bonded to a surface 2A of the layer 2. Layer 2 further contains the back side 22 玖, Description of the invention Surface 2B. In general, Layer 1, Layer 2 or both layers 1 and 2 are processed to define areas of weak junction 5 and strong junction 6 and are subsequently joined, To form the plurality of selectively bonded substrates 100, These areas where the weak joint 5 is in a case where a useful device or structural processing is allowed, It includes micro-electro-mechanical systems and / or other useful devices or structures.  In general, 'layers 1 and 2 are phase-phased. That ’s ’layers 1 and 2 make up compatible heat, Mechanical and / or crystalline properties. In some preferred embodiments, Layers 1 and 2 are the same material. of course, Different materials can also be used, But it is better to make a choice based on compatibility.  One or more regions of layer 1 are defined as one or more structures such as microelectronics that can be formed in or on a substrate region. These areas may be any desired pattern, As explained further here. then, Selective areas of layer 1 can be processed to minimize the bonding to form the weak bonding area 5. on the other hand, The corresponding area of layer 2 can be processed (together with or instead of layer 1) to minimize the joint. Another option involves treating layer 1 and / or layer 2 in areas that are not selected to form the structures, In order to improve the bonding strength in the strong bonding region 6.  After layer 1 and / or layer 2 are processed, the layers can be aligned and joined. The joining can be performed by any suitable method as further described herein. Also, the alignment may be mechanical, Optical or a combination thereof. It should be understood that straightening at this stage may not be important, Because there is usually no structure formed on the layer. but, If both layer 1 and layer 2 are processed, 'alignment may be necessary to minimize vibrations in the area of the substrate originating from this selectivity.  玖, SUMMARY OF THE INVENTION The multi-layer substrate 100 can be processed, To form a microelectromechanical system or any other desired structure in or on layer 1. therefore, The multi-layer substrate 100 is formed, It allows users to process any structure or device using traditional manufacturing techniques or other technologies that have become known as the development of various related technologies. Certain manufacturing techniques can subject the substrate to extreme conditions, Such as high temperature, pressure, Harsh chemicals or combinations thereof. therefore, The multi-layer substrate 100 is preferably manufactured to withstand these conditions.  Mechatronic systems or other useful structures or devices can be formed in or on Area 3, Partially or substantially overlaps the weak junction area 5. Therefore, Zone 4, Partially or substantially with a strong joint area 6, There is usually no structure in or on it. After the microelectromechanical system or other useful device is formed in or on layer 1 of the plurality of substrates 100, Layer 1 may be subsequently joined. This separation can be performed by any suitable method, Such as stripping,  There is no need for the MEMS or other useful devices to perform unfavorable delamination techniques directly. Because micro-electro-mechanical systems or other useful devices are usually not formed in or on area 4, These areas can be separated, Such as ion or particle implantation, This does not damage the structures formed in or within the region 3.  To form a weak junction area 5, Surface 1A, 2 A or both can be processed at the position of the weak junction, To form substantially no joints or weak joints.  on the other hand, The weakly bonded areas 5 may be left untreated, The strong bonding is caused by the processing of the strong bonding region 6. The region 4 partially or substantially overlaps the strong bonding region 6. In order to form the strong bonding region 6, Surface ία,  2A or both can be processed at the location of the strong junction area 6. on the other hand,  553891 玖, DESCRIPTION OF THE INVENTION The strong bonding area 6 can be left untreated, Weak bonding is caused by the processing of the weak bonding region 5. Furthermore, Zones 5 and 6 may be processed by different processing techniques, These treatments may differ in quality or quantity.  After the treatment 5 of one or both of the weak joint region 5 and the strong joint region 6, Layers 1 and 2 are joined together, To form a substantially complete multilayer substrate 100. therefore, As formed, The multilayer substrate 100 can withstand the severe environment of the end user, for example, And a structure or device 'is formed therein or thereon, in particular in or on the region 3 of the layer 1.  The phrase "weak association, , Or "weak engagement, , Usually refers to separation between layers, or by separation such as 10 peeling or other mechanical, heat, Light, Pressure or a separation technique comprising a combination of at least one of the foregoing separation techniques can quickly recover the bonding between portions of a layer. These separation techniques have minimal casting defects or damage to layer 2, Especially in the vicinity of the weak joint area 5.  The processing of one or both of the group of weak joints 5 and the group of strong joints 6 can be performed by various methods. The point of this process is that the weakly bonded region 5 is easier to separate than the strongly bonded region 6 (as described in the subsequent separation step described further herein). During separation, This will minimize or avoid damage to Area 3, It may contain useful structures on it. Furthermore, The inclusions in the strong bonding region 6 enhance the mechanical integrity of the multi-layer substrate 100. therefore, When 20 removes useful structures in or on it, Handling of layers can be minimized or eliminated.  The special type of treatment performed by one or both of the group of weak joints 5 and strong joints 6 is usually based on the materials selected. and, The choice of bonding technology for layers 1 and 2 may be based on, At least in part, Choose ^ Li Fang 25 553891 玖, Description of the invention In addition, The subsequent separation is based on Joining method, material, The type of useful structure depends on factors that exist or contain a combination of at least one of the foregoing. In some embodiments, The selective treatment, The combination of bonding and subsequent disengagement (i.e. the end user makes a useful structure in zone 35, Or an intermediate component in a higher-order device) can eliminate the need for cracks to propagate layer 丨 separated by layer 2 or mechanically thinned to remove layer 2, It is better to eliminate crack propagation and mechanical wear. therefore,  The underlying substrate can be reused with minimal or no treatment, Because of traditional doctrine, Crack propagation or mechanical thinning can damage layer 2, So that 10 gets it without further substantial processing, Basically useless.  A processing technique that may depend on the surface roughness between the weakly bonded areas 5 and the strongly bonded areas 6. The surface roughness can be found on the surface ia (Figure 4), Surface 2A (Fig. 5) or both ιA and 2a were modified. In general, These weak joint areas 5 have a higher surface roughness 15 degrees 7 than the strong joint areas 6 (Figures 4 and 5). In semiconductor materials, For example, the weak junction regions 5 may have a surface roughness greater than about 0.5 nanometers (nm), At the same time, the strong bonding areas 4 may have a lower surface roughness, It is usually less than about 0.5 nm. In another embodiment, The weak bonding regions 5 may have a surface roughness larger than a large mnm, Moreover, these strong bonding areas 4 may have a low surface roughness, It is usually less than about 1 nm. In another embodiment, The weak bonding regions 5 may have a surface urbanization greater than about 5 nm, And these strong bonding areas 4 may have a lower surface roughness,  It is usually less than about 5 nm. The surface roughness can be determined by rhenium (for example, in a hydrogen hydroxide solution or a hydrogen fluoride solution) or by a deposition method (for example, low pressure chemical vapor phase 26 553891 玖, Description of the invention Deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD)). For example, ‘the bonding strength and the surface sugar content are in Gui ’s“ Selective wafer bonding by controlling surface roughness ”, Journal of The Electrochemical Society, It is more fully described in Vol. 148 (4), pages G225-G228 5 (2001), It is here incorporated by reference.  In a similar way (where similar states are marked with similar reference numerals as in Figures 4 and 5), A porous region 7 may be formed in these weakly bonded regions 5, And the strong bonding area 6 may still be untreated.  10 Therefore, Due to its porous nature, The layer 1 has a minimum joint with the layer 2 at the positions of these weak joint regions 5. The porosity can be on the surface (Figure 4), Surface 2A (Figure 5) or both surfaces 1A and 2A are modified. In general, The weak joints 5 have higher porosity than the strong joints 6 at the porous regions 7 (Figs. 4 and 5).  15 Other processing techniques may depend on the selectivity of these weak junctions 5 (on surface 1A (Figure 4), 2A (Figure 5) or both surfaces 1A and 2A),  Deposition of photoresist or other carbon-containing materials, such as polymer-based decomposable materials, is then performed in the etched area. one more time, Areas of similar status are marked with similar reference numerals as in Figures 4 and 5. Regarding the joining of layers 1 and 2,  20 It is preferably carried out at a temperature sufficient to decompose the carrier material, The weak connection σ & Domain 5 includes a porous broken material 'so that the bonding between layers 1 and 2 of the weak bonding areas 5 is very weak compared to the bonding between layers 1 and 2 of the strong bonding areas 6 of. Anyone familiar with the art will understand that ‘depending on the environment, Does not heat exhaust gas, Pollution or not the same 27 553891 玖, BRIEF DESCRIPTION OF THE INVENTION A decomposing material that dirtys the substrate layer 1 or 2 or any useful structure that will be formed in or near the region 3 will be selected.  A further processing technique may be the use of radiation to obtain strong joint areas and / or weak joint areas5. In this technique, With neutrons, ion,  5 particle beam or combination of radiation layers 1 and / or 2 thereof, To achieve the required strong and / or weak joints. for example, Such as helium ions (He +), Particles of hydrogen ions (Η +) or other suitable ions or particles, Electromagnetic energy or laser beams can be applied to these strong bonding areas 6 (on the surface 1A (Figure 10), 2A (Figure 11) or both 18 and 28). It should be understood that for the purpose of leaving the layer, Radiation methods differ from ion implantation in that the dose and / or implantation energy is very low (for example, Suitable for delamination use in the order of one hundredth or one thousandth).  An additional processing technique includes the Use of a slurry of solid composition and decomposable composition on both 2A or 1A and 2A. The 15 solid composition may be, for example, alumina, Silicon oxide (Si〇 (x)), Other solid metals or metal oxides or other materials that minimize the bonding of these layers 1 and 2. The decomposable composition may be, for example, polyethylene glycol (PVA) or other suitable decomposable polymers. usually, Mud 8 is applied to the surfaces 1A (Figure 2) of these weakly bonded areas 5, 2A (Figure 3) or both 1A and 20 2A. after that, Layers 丨 and / or 2 can be heated, Preferably in an inert environment, To decompose the polymer. therefore, The porous structure (composed of the solid composition of the mud) remains in the weakly bonded areas 5, And once joined, Layers 1 and 2 are not bonded to these weakly bonded areas 5.  Yet another processing technique includes etching the surfaces of the weak bonding areas 5 28 553891 玖, Description of the invention. During this etching step, Column 9 is defined in the tables of these weak junction areas 5 (Figure 8), 2A (Figure 9) or both 1A and 2A. The columns can be defined by selective narration, Leave the columns behind. The shape of these columns may be triangular, Triangular cone, Rectangle or other suitable shapes.  5 On the other hand, The pillars can be grown or deposited in the etched area.  For this material, Because there are fewer joints, The total bonding strength at the weak bonding regions 5 is lower than the bonding at the strong bonding regions 6.  There is another processing technique including an empty area 10 (Figures 12 and 13), for example, It is 5 layers 1 in this weak junction area (Figure 12), 2 (Figure 13) In 10, by etching, Mechanical or both. therefore, When the first layer is connected to σ at the first layer 2 of xr, Compared with this strong joint area 6, The void areas 10 will minimize the joint, It facilitates subsequent separation.  Another treatment technique includes surface 1A (picture 2) 2A (Figure 3) or 1A and 2A of these weakly bonded areas of one or more metal regions 8 15 is used. for example, Metals include, But not restricted, copper, gold, Platinum or any combination or alloy thereof may be deposited on these weakly bonded areas 5. Regarding the joining of layers 1 and 2, The weakly bonded areas 5 will be weakly bonded.  Some of the strong joint areas may still be untreated (where the weak joint area 5 and the strong joint area 6 ’the difference in joint strength provides the required ratio of strong joints to 20 weak joints), Or may be processed as described above or below, To cause firm adhesion.  Another treatment technique includes 1A (Figure 10) on the surfaces of the strong bonding areas 6, Use of one or more adhesion promoters 11 on 2A (Figure 11) or both 1A and 2A. Suitable adhesion promoters include, But not restricted, Titanium oxide 29 553891 玖, Description of the Invention TiO (x), Oxidation buttons or other adhesion promoters. on the other hand, Substantially subsequent accelerators can be used on all surfaces 1A and / or 2A, One of the metallic materials is placed between the adhesion promoter and the opposing surfaces 1A and / or 2 A of the weakly bonded areas 5 (depending on the location of the adhesion promoter) 5. therefore, Immediately after joining, the metallic material will avoid strong joining. In these weak joining areas 5, on the contrary, The adhesion promoter remaining in these strong bonding areas 6 promotes strong bonding.  Yet another treatment technique includes providing areas that change hydrophobicity and / or hydrophilicity. for example, The hydrophilic region is particularly useful for the strong bonding region 6 'because, for example, broken materials can spontaneously bond at room temperature. Hydrophobic and hydrophilic joining techniques are known at room temperature and high temperature. for example,  Such as in Tang (Q · Y · Tong), Goesle, Semiconductor wafer bonding ‘Science and Technology, Pages 49-135  John Wiley and Sons, New York NY 1999 It was incorporated here! 5 References.  Yet another processing technique includes one or more peeling layers that are selectively irradiated. for example, One or more release layers can be placed on the surface  / Or 2A. No radiation, The release layer acts as an adhesive. Regarding the exposure of these weakly bonded areas 5 to radiation such as ultraviolet light, This adhesion 20 characteristic can be minimized. The useful structures can be formed in or on the weakly bonded region 5, And subsequent UV radiation steps or other separation techniques can be used, In order to separate the layers 丨 and 2 at the strong bonding areas 6, an additional processing technique includes an implanted ion 12 (Figures 6 and 7), Root 30 553891 玖, Description of the invention The layer allowed in the weak area according to the heat treatment (Figure 6), Most microbubbles 13 are formed in layer 2 (Figure 7) or both layers 1 and 2. therefore, When layers 丨 and 2 are joined, The weakly-bonded regions 5 have fewer bonds than the strong-bonded regions 6, The subsequent separation of the layers 1 and 2 in the weakly bonded regions 5 is easily performed. 5 Another processing technique includes an ion implantation step and an etching step subsequent thereto. In one embodiment, This technique is essentially performed by ion implantation over the entire surface 1B. Since then, The weak bonding regions 5 can be selectively etched.  A method for removing defects by removing selective etching is described in Simpson 10 et al. , , Electrochemical and Solid-State Letters, Vol. 4 (3), pp. G26-G27, It is here incorporated by reference.  Further processing techniques enable selective placement of these weakly-bonded regions 5 and / or strong-bonded regions 6, It has one of the characteristics of radiation absorption and / or reflection. 15 or more layers, May be based on a narrow or wide wavelength range. For example, ’a layer or layers that are selectively placed in the strong junction area 6 may have a bonding property immediately after exposure to certain radiation wavelengths, This layer is made to absorb radiation and to bond layers 1 and 2 in a strong bonding region 6.  A person familiar with the art will understand that not only the additional processing technology can be used, Furthermore, a combination comprising at least one of the aforementioned processing techniques can also be used. but, A key characteristic of any of the processes used is the ability to form one or more weak junctions and one or more strong junctions.  The geometry of the interface between the weak junction areas 5 and the strong junction areas 6 at layers 1 and 2, May be based on including, But not restricted, On area 3 or 31 553891 玖, Description of the invention Selected separation / joint type, The factors selected for the processing technique vary with other factors. As shown in Figure ‘16, The areas 5, 6 may be concentric. # 然 ， A person familiar with the art will know that any geometric trait can be selected. In addition, The ratio of weakly joined 5 areas to strongly joined areas may change. In general, This ratio provides sufficient engagement (that is, In the strong bonding regions 6) so as not to contain the integrity of the multi-layer structure 100, Especially during structural processing. This ratio is better and is also used to maximize the useful area for structural processing (i.e. weak junction area 5).  10 is substantially after one or both of the surfaces 1A and 2A in the weak bonding region 5 and / or the strong bonding region 6 as described above, Layers 2 are joined together to form a substantially integrated multilayer substrate 100. Layers 丨 and 2 can be joined together by one of several technologies and / or physical phenomena, It includes, but is not limited to, Eutectic, Fusion, Anode, vacuum, Van der Waal, Chemistry followed by 15 Hydrophobic phenomenon, Hydrophilic phenomenon, Hydrogen bonding, Columbus, Capillary force,  Very short-range forces or a combination of at least one of the foregoing joining techniques and / or physical phenomena. of course, It will be apparent to one skilled in the art that the bonding technique and / or physical phenomenon may be partially dependent on one or more processing techniques used, A form or entity of useful structure formed in or on it, Depending on the intended separation method or other factors.  therefore, A plurality of layers of substrate 100 may be used to form a microelectromechanical system or one or more other useful structures in area 3 with it, It substantially or partially overlaps the weak junction region 5 at the interface of the surfaces 1A and 2A. These useful structures may include one or more active or passive elements, Device,  32 553891 玖, Description of the invention tool, Circuit, Other useful structures or combinations containing at least one useful structure described in these months. E.g, The useful structure may include an integrated circuit or solar cell. of course, A person familiar with the art will know that various micro-technology and nano-technology devices may be formed, It includes MEMS for various purposes, Such as sensors, switch, Mirror, Micro motor, Micro fans and other MEMS.  After one or more structures have been formed on one or more selected regions 3 of the layer, Layers can be separated by various methods. It can be appreciated that because the structures are formed in or on the regions 4, Its portion 10 points or substantially overlaps the weak junction area 5, The separation of layer 1 can occur at the same time as the typical damage to the structure with the separation, Defects or deformations such as structures can be minimized or eliminated.  Separation can be accomplished by a variety of different known techniques. In general, The separation may be based on, At least in part, The processing technology, Joining technology, The type of useful structure depends on the entity or other factors.  In general, Speaking of Figures 17-28, Separation techniques may form microbubbles at a reference depth based on the implantation of ions or particles, It is usually equivalent to the thickness of layer 1. These ions or particles may be derived from oxygen, hydrogen, Helium or other particles 14. This combination was then exposed to strong electromagnetic radiation, heat, Light (infrared or ultraviolet for 20 examples), Stress or a combination of at least one of the foregoing, Causing the particles or ions to form the microbubbles 15, And finally swell and delaminate layers 1 and 2. The implantation and optional heat, The mechanical separation step can also be performed after light and / or pressure (section 19, twenty two, 25, Figure 28), for example, In the plane of these layers 1 and 2, Parallel to these layers 丨 and 2 planes,  33 553891 玖, DESCRIPTION OF THE INVENTION In the direction of other angles of the planes 1 and 2 of these layers, In the peeling direction (19th, twenty two, 25, 28), or a combination thereof. Ion implantation for thin layer separation will be explained in more detail, For example, in U.S. Patent No. 6, Cheung, etc., 027, No. 988, "Method Of Separating Films From Bulk Substrates By Plasma Immersion Ion Implantation", It is here incorporated into the reference. Typical hydrogen implantation conditions are a dose of 5 x 10-16 cm_2 and an energy of 120 kiloelectron volts. For the conditions above, It can be split from the wafer by about 1 micron layer thickness. The thickness of this layer is only a function of the depth of the implant, It is 90 Angstroms (A) per kilovolt of energy π for hydrogen in silicon. The implantation of high-energy particles will significantly heat the material. When hydrogen is implanted, Preferably, by reducing the beam current by a factor of 1/2 or more, Or, avoid blistering by holding and cooling the wafer. Separation with a lower implantation dose of hydrogen can already be done using co-implantation of helium I4 15 or boron (higher performance copper process) 15. This technology has been used to commercialize silicon-on-insulator (SOI) wafers, It is used in machining microcomputer electrical equipment, The 3-dimensional integration of optical devices with more devices and 3 microelectronics leaves huge possibilities.  The surface quality of this cleaved surface is reported to be excellent I6. A thin layer 20 is separated along the micro-cracks formed by the hydrogen ion implantation. The separation can be performed by a heat treatment that increases the internal pressure of hydrogen microbubbles in the crystal lattice, Or mechanical stress can be used, To start and spread the crack. Microelectronic device pairing; 5374564 ^ (1994 〇 34 553891 玖, Description of the invention Ingression damage is very sensitive, Therefore, this technique is particularly used at the beginning of preparation. And never on a completed or in-process wafer.  In addition, Passive ion implantation results in more diffusion implant / height profile when passing through a structured wafer. These incident ions will experience different materials and ground shapes. Therefore, the range parameter will be related to the wafer position.  Especially referring to Figures 17-19 and 20-22, The interface between layers 1 and 2 may be selectively implanted with ions or particles 16, In particular, microbubbles 17 are formed in these strongly bonded regions 17. In this way, The implantation of particles 16 in region 3 (with one or more useful structures in or on it) is reduced to a maximum of 10), This reduces the possibility of repairable or irreparable damage that may occur to one or more useful structures in area 3. Selective implantation can be performed by selective ion beam scanning of the strong junction area 4 (Figures 17-19) or the masking of these areas 3 (Figures 20-22). Selective ion beam scanning refers to the mechanical operation of the structure 100 and / or the device used to introduce ions 15 or particles to be implanted. As is known to those skilled in the art, Various devices and technologies can be used for selective scanning, It includes, But not limited Focused ion beam and electromagnetic beam. Furthermore, Various masking materials and techniques are also known in the art.  Referring to Figures 23-25, Implantation may be performed substantially across the entire surface 20 or 2B. The appropriate degree of implantation depends on the target and implant material and the desired depth of implantation. therefore, Layer 2 is much thicker than Layer 1, It may not be implantable through surface 2B; but, If layer 2 is a suitable implant thickness (for example, Within the range of energy that can be implanted), Implantable Smart cut surface quality β 35 553891 玖, DESCRIPTION OF THE INVENTION A translucent surface 2B may be required. This will minimize or eliminate the possibility of repairable or irreparable damage to one or more useful structures in area 3.  In one embodiment, Referring to Figure 15 and Figures 26-28 at the same time, The abutment region 6 is formed around the outside of the interface between the layers 1 and 2. therefore,  In order to separate the layers 1 and 2, the ions or particles 16 can be implanted For example, 'the microbubbles 17 are formed at the interface between layers 1 and 2 through region 4. Better use of selective scanning, The structure 100 can be rotated (shown by arrow 20), A scanning device 21 may be rotated (shown by arrow 22), Or a combination thereof 10. In this embodiment, Another advantage is to provide the end user with the flexibility to choose useful materials in or on the structure. The size (i.e., width) of the strong bonding region 6 is suitable for maintaining the mechanical and thermal integrity of the multilayer structure 100. The size of the strong bonding area 6 is preferably the smallest, This maximizes the area of the weak junction area for structural processing. For example, 15 The strong bonding area 6 may be one (1) micrometer on the order of eight (8) inches.  Furthermore, Separate layers by layer 2! can, for example, Starting with other traditional methods such as money engraving (bordered surfaces), The last name engraved through the strong bonding area 6 is formed. In such an embodiment, This processing technology is particularly suitable,  For example, the strong bonding region 6 is treated with an oxide layer having a high selectivity to the overall material (ie, 20 is the layer m2). It is preferable that the weak bonding regions 5 do not require etching, And the layer 1 is separated by the layer 2 at the position of the weak junction area 5, Because of this selective treatment, Or its shortcomings, The bonding at the step of bonding layer i to layer 2 can be avoided.  on the other hand, Crack propagation may be used to initiate the separation of layers 1 and 2.  36 553891 玖, DESCRIPTION OF THE INVENTION Once again, The separation is preferably only at those strong joining areas 6, Because the joints in these weak joint areas 5 are limited. Furthermore, Separation can be started by etching (perpendicular to the surface), Is conventionally known, It is preferably confined to the position of area 4 (that is, partially or substantially overlaps with the strong joint area 6).  Layers 1 and 2 may be the same or different materials, And may contain materials, Including but not limited to, Plastic (e.g. carbonate), metal, Semiconductor, Insulator, Single crystal, Amorphous, No crystallization, Biological (such as a DNA-based film) or a combination comprising at least one of the foregoing types of materials. For example 1〇, Special material types include silicon (for example, Such as silicon nitride, SiC single crystal 'polycrystalline, No crystallization, Polysilicon and derivatives),  Gallium arsenide, Indium phosphide, Cadmium selenide, Cadmium telluride, Silicon germanium, Gallium arsenic phosphide,  Gallium nitride, Carbide eve, Gallium Ming, Noodles, Recorded inscriptions, Deified marriage, gallium, Zinc sulfide, Aluminum nitride, Titanium nitride, Other three A-five A (IIIA-VA) family 15 materials, Three B (IIIB) materials, Six A (VIA) materials, sapphire, Quartz (crystal or glass), diamond, Silicon oxide and / or silicate-based materials or a combination comprising at least one of the foregoing materials. of course, Processing of other types of materials may benefit the methods described here, A multi-layer substrate 100 is provided with the required components. The preferred materials that are particularly suitable for the methods described herein include 20 semiconductor materials (for example, Shi Xi) as layer i, And semiconductor materials (for example, Shi Xi) as layer 2, Other combinations include, But not restricted, Semiconductor (layer υ or glass (layer 2), · Semiconductor (layer 1) on carbide eve (layer 2); Semiconductor (layer u; on sapphire (layer 2)) Nibbling on the Sapphire (layer magic (layer ^);  Gallium nitride (layer U) on glass (layer 2); Gallium nitride on carbide eve (layer 2) 37 553891 玖, Description of the invention (layer 1); Plastic (layer υ, The layers 丨 and 2 may be the same or different plastics; And plastic (layer 丨) on glass (layer 2).  Layers 1 and 2 may be derived from a variety of different materials, These include wafers or fluid materials that are deposited to form thin film and / or substrate structures. When the starting material 5 is in the shape of a wafer, Any conventional method can be used to produce layers 1 and / or 2. for example, Layer 2 may consist of a wafer, And layer i may contain part of the same or different wafers. Parts of the wafer's constituent layers 丨 may originate from mechanical thinning (for example, Mechanical grinding, Cutting, Throw light, Chemical mechanical grinding, Buff-stop or a combination comprising at least one of the foregoing grinds 10), Crack propagation, Ion implantation followed by mechanical separation (e.g. crack propagation, Perpendicular to the plane of the structure 100, Parallel to the plane of the structure, In the peeling direction, Or a combination thereof) followed by thermal implantation, Light and / or pressure induced layer separation, Chemical etching or the like. Furthermore, For example, one or both of layers 1 and 2 can be deposited by chemical meteorology, An epitaxial growth method or a similar method is used to deposit or grow.  An important benefit of this immediate method and the production of multilayer substrates with MEMS or other useful structures thereon is that the useful structures are formed in or on these regions 3, It partially or substantially overlaps this weak joint area 5. When this layer is removed by layer 2, This essentially makes it useful, The possibility of damage to the structure is minimized or eliminated. This separation step often requires intrusion (for example, Ion implantation), Applying force or other techniques needed to separate layers 1 and 2. because, In some embodiments, These structures in or on Area 3 do not require local intrusion, Applying force or other processing steps that may have repairable or irreparable damage to these structures,  38 553891 玖, Description of the invention Layer 1 can be removed, At the same time, specially derived structures do not require subsequent processing to repair these structures. The areas 4 which partially or substantially overlap the strong joining areas 6 usually have no structure thereon, These differences can therefore be inserted or applied without damaging the structures.  5 This layer 1 can be removed as a self-supporting film or as a supported film. for example, The lift layer is usually used to attach to the layer. So that layer 1 can be removed by layer 2, It is still supported by this lifting layer. usually, The pull-up layer may be used to substantially place the film or a portion thereof (eg, having one or more useful structures) on a desired substrate, Other processed 10 films or one of the two remained on the lift layer. One such lifting layer was disclosed in US Provisional Patent Application No. 60/326432, filed on October 02, 2001, Title "Apparatus and method for processing fragile objects and its manufacturing method", , It is here incorporated by reference.  The benefit of this urgent method is that the materials making up layer 2 can be reused 15 or recycled. for example, By any known method, A single wafer can be used to produce layer 1. The derived layer 1 can be selectively bonded to the remaining portion (layer 2) as described above. When the film is separated, Using the remaining portion of layer 2, a thin film to be used as the next layer can be obtained.  This can be repeated until it is no longer feasible or the remaining portion of layer 2 is actually used to generate a thin film for layer 1.  As discussed above, MEMS devices are a natural choice for vertical stacking. The challenge of 3D integration of the MEMS sensor suite is easier to deal with than in microelectronics. For MEMS devices, The critical size is large and the total number of inputs / outputs is small. Vertical interconnection 39 553891 玖, Invention description can be made bigger, It has a significant positive impact on the reliability of vertical connections between devices that do not adversely affect the increase in chip size. Wafer bonding is an established step in the fabrication of MEMS. For MEMS sensors, Electricity consumption can be quite low, Makes thermal management much easier. for example,  5 In some embodiments, The average power consumption can be less than 100 microwatts (3 volts, Average current consumption < 30 micro amps), except for the thermal management of stacking kits which are important issues. Now that the thin device layer is transferred, the vertical interconnection can be easily performed by through-hole technology for MEMS. The multilayer substrate can economically stack the rebuttal devices into a single package. The thinness of the devices can be peeled from the crystal circle scale of the multilayer substrate by the device layer. So 'according to the method here, the device layer can be completely removed from the bonded wafers. Due to the selective bonding method described above, this method does not require ion implantation through the completed wafer, post-polishing the wafer, or etching the 15 wafer. Toward the plane, controlled cracks (for example, peeling) will separate the thin, completed device layer by the wafer body. The transfer of this device can reach wafer scale. During thin layer transfer, the device layer is bonded to another wafer with the same or different devices, or to any surface. These devices can be other MEMS sensors, or the wafer may contain 20 ASIC controllers or memory chips. This method eliminates design constraints and allows the selection of the inductor to be discontinuously optimized. The agency has an open architecture that allows the selection of the best grade sensors. Design changes to the kit can be made with minimal cost by simply replacing one or more layers. The sensor may be provided as a commercially available sensor, 40 553891 玖, description of the invention, or may be designed to be used separately with a wafer size designed to conform to the substrate wafer with the commercial sensor Manufacturing of wafers or wafers. The starting wafer is designed to have a separation plane for easy removal of the device layer, and is transferred to the main crystal B, where it can be melted and bonded. If required, additional layers of the inductor and / or control circuitry can be added. Post-grinding is not necessary. The wafer bond pad is designed to be vertical. By designing parallel pins, the total number of pins can be reduced as much as possible. Because these layers are very thin, the through-hole groove is a practical solution for forming a three-dimensional interconnection. Furthermore, it can be an edge connection design. After optional passivation, the wafer is ready for backside fabrication (slicing, wire bonding, etc.). Referring now to Figures 29-34, the process steps for forming a vertically integrated MEMS-based device are shown. Figure 29 shows a release layer 51 (e.g. equivalent to the upper layer) having a majority of voids 52 (15 in these weakly bonded areas) intended to be marked with activatable micromirrors, actuations, or other MEMS. Side and top icon. It should be noted that some devices may not require empty areas to allow motion, and further such empty areas may be incorporated into layers containing the MEMS itself. Figure 30 shows a side and top illustration of a release layer 53 (e.g., equivalent to layer 1 above). For example, with a majority of activatable micromirrors (in these 20 weakly bonded areas), Actuators or other microelectromechanical systems 54 processed on it known in the art. Figure 31 shows another optional release layer 55 (e.g. equivalent to the above) having a plurality of cavities 56 (in these weakly bonded areas) intended to be labeled with activatable micromirrors, actuators, or other MEMS. The side and top of layer 1) are shown. Fig. 32 shows a side view and a top view of 41,553,891, description of the invention, peeling layer 57 (e.g., equivalent to layer 1 above). The majority of logic devices 58 (in these weak junction areas). Fig. 33 shows the side and top illustrations of a peeling layer 59 (e.g. equivalent to layer 1 above), for example 5 saying "has a snout and the MEMS shown in Figs. 30 and 32 respectively, and The logic device is coupled to operate a majority of the memory devices 60 (in these weakly bonded areas). Then, each of the individual device (or void) layers in Figures 29-33 are stacked as shown in Figure 34 to form a combination of logic and memory (10 and others that are obvious to those skilled in the art). Functionality) Most vertically integrated MEMS devices. The edges of the layers (equivalent to the strong junction area and shown by dotted line 21) can be removed, while the individual vertically integrated MEMS device (Figure 35) including joint logic and memory can be removed at dotted line 22 Die cutting. 15 Device integration must address the issue of mixed yield loss. Consider a stack with a number of layers equal to η. If each device in the stack is manufactured with a yield of γ%, the yield for this integrated system is an increase of η to the power of γ. As the number of layers increases, the yield of the system becomes very small very quickly. For a layer stack that makes up a device with a 90% yield, approximately 40% of the 20 stack will contain a non-functional die. This embodiment is similar when this embodiment considers the yield loss of stacking integration when integrating different types of processing flows on a single wafer area. MEMS integration plans are better by using a known good die (ICGD), by establishing a capacity that allows the package to be overwhelmed, even if a special 42 553891 发明, invention states that other devices are not functional, By having a cost structure that can support low yields, mixed yield losses are allowed. As mentioned previously, the use of known good grains is an expensive option limited to high reliability and costly applications. Designing extra devices can adversely affect chip area, power consumption, operation complexity, and total pin count. Vertical stacking can mitigate the adverse effects on the area by stacking the devices. By taking advantage of this vertical size, the devices can be stacked without increasing package size and cost. The advantages of the MEMS and the 10 methods used to form the MEMS described here include: economical, ability to use the best grade of sensors (no exchange during device processing), open architecture And they can be extended to hybrid MEMS_Microelectronics Kits. A vertically integrated machining process is provided that can make an open architecture MEMS sensor kit. In particular, a sensor kit with a combination of temperature, 15 pairs of humidity, and 3-axis vibration measurement will be designed, but the method is expected to be generally applied to the integration of all sensor types, as well as to MEMS plus electronic controllers Wafer combination. A 3D integrated sensor kit using these methods described here is also available. In one embodiment, a commercialized sensor may be selected for a base 20 (lift) wafer. The entire wafer can be processed, including the required die size and input / output planning. The remaining inductors may be designed for the actual size and bonding of commercial grains. A starting wafer is also provided after the device is manufactured, where the starting crystal is 43 553891 玖, the description of the circle includes a part of a 3D MEMS system such as a MEMS kit. Furthermore 'provides a method of manufacturing such a starting wafer to facilitate the removal and transfer of wafer-scale devices. The 3-dimensional MEMS may have through-hole connections or edge connections, as known to those skilled in the art. In addition to MEMS and hybrid MEMS kits, these methods and structures can be extended to high-density microelectronic stacks. Examples of the former are very high density memory stacks (petabytes) and a combination of memory and logic chips. 10 This method will enable rapid design prototypes and production of any type of sensor kit. This method can be extended to ultra-high-density electronic packages and high-density combinations of micro-electro-mechanical systems with ASIC controllers and memory chips. The electromechanical system has an open architecture that allows any individual component to be changed at any time with minimal redesign and mask changes. 15 The application of MEMS sensors has been discussed above. As discussed, MEMS sensors are expected to have a very high mixed growth rate of 35%. The cost-improved vertical integration structure will open many phase applications for MEMS technology. When the preferred embodiment has been shown and described in steel, various modifications and substitutions can be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the present invention has been described by way of illustration and not limitation. [Brief description of the drawings] FIG. 1 is a schematic diagram illustrating an embodiment of a layered structure of a microdevice which is suitable for forming a micro-electromechanical system and other unions. A layer suitable for inclusions in a micro-electromechanical system; Figure 3 depicts a support layer according to an embodiment; 5 Figure 4 depicts a layer for inclusions suitable for a MEMS system according to an embodiment; 5 is a description of a support layer according to an embodiment; FIG. 6 is a description of a content layer suitable for a micro-electromechanical system according to an embodiment; 10 FIG. 7 is a description of a support layer according to an embodiment; FIG. 8 FIG. 9 describes a layer of contents suitable for a micro-electro-mechanical system according to an embodiment; FIG. 9 illustrates a support layer according to an embodiment; FIG. 10 illustrates a content of a micro-electro-mechanical system according to an embodiment. Figure 11 depicts a support layer according to an embodiment; Figure 12 depicts a layer of inclusions suitable for a micro-electromechanical system according to an embodiment; Layer 13 depicts a support according to an embodiment Layer; 2〇 14 is one of the joint geometry used for the structure of Fig. 1 Fig. 15 is another embodiment of the joint geometry used for the structure of Fig. 丨 Fig. 16 is used for the joint structure of Fig. 丨Another aspect of the joint geometry of the structure of the figure; / 45 553891 发明, description of the invention Figure 17 describes a separation step by selectively planting one according to an embodiment; Figure 18 describes the step according to an embodiment An intermediate structure after the step 5 FIG. 19 is a step of peeling off the structure of FIG. 18; FIG. 20 illustrates a separation step by using selective implantation through a mask structure according to an embodiment; FIG. 21 is An intermediate structure after this step is described according to an embodiment; FIG. 22 illustrates the steps of stripping the structure from FIG. 21; FIG. 23 illustrates separation by using one of the non-selective implants according to an embodiment Fig. 24 illustrates an intermediate structure after the steps of Fig. 23 according to an embodiment, 15 Fig. 25 illustrates the steps of peeling off the structure of Fig. 24; Fig. 26 illustrates the use of an embodiment by Use selective planting around Fig. 27 illustrates an intermediate structure after the steps of Fig. 26 according to an embodiment; Fig. 28 illustrates the steps of peeling off the structure of Fig. 27; Fig. 29 shows a record to be recorded Side view and top view of a peelable layer of an activatable micromirror, actuator, or other microelectromechanical system; Figure 30 shows a side view and a top view of a peelable layer, such as a plurality of actuated micromirrors, actuated Device or other MEMS processing on it; 46. Description of the invention Figure 31 shows another peeling layer with a plurality of voids to record activatable micromirrors, actuators or other MEMS; Figure 2 shows a stripped layer with a plurality of logic devices to be operatively coupled to the combined MEMS device shown in Figure 30; Figure 33 shows a stripped layer with a plurality of memory devices to be operatively coupled to The combined MEMS device and logic device are shown in Figures 30 and 32, respectively; Figure 34 shows a plurality of vertically integrated MEMS devices, including a wafer-level combined logic and memory; and Figure 5 shows another vertically integrated MEMS device. [Representative symbol table of the main elements of the drawing] Layer 5 ... Weak bonding area 1A ... Surface 1B of layer 1 ... Back surface 2 of layer 1 ... Layer 2A ... Surface 2B of layer 2 ... Back surface of layer 2 ... Weak bonding area 4 ... Strongly bonded area

6 ... Strongly bonded area 16 ... Ions or particles 17 ... Strongly bonded area / microbubble 20 ... Rotational direction of the structure 100 ... Scanning device 22 ... Rotational direction of the scanning device 100 ... Most bases Wood 47

Claims (1)

553891 Patent application scope 1. A micro-electro-mechanical system layer, in which the micro-electro-mechanical system is selectively bonded to a substrate layer before the fabrication of the micro-electro-mechanical system on the layer, wherein the selective bonding is included in At least one strongly bonded area and at least one weakly bonded area at the interface between the MEMS and the substrate layer, most of which are formed on the surface of the MEMS layer in the weakly bonded area or on the surface of the MEMS layer. Among them, and further, the MEMS layer can be removed from the substrate by mainly separating in the strong bonding area. 2. The micro-electro-mechanical system layer according to item 1 of the patent application scope, wherein the micro-electro-mechanical system layer is selectively bonded to the substrate layer around an interface between the micro-electro-mechanical system layer and the substrate layer. 3. A type of vertically integrated micro-electro-mechanical system, including the micro-electro-mechanical system layer such as item 1 of the scope of patent application and a joint control layer. 4. The vertically integrated micro-electro-mechanical system according to item 3 of the patent application scope, in which 15 the joint control layer is composed of logic, memory, thermal control, a micro-electro-mechanical system formed on or in the micro-electro-mechanical system layer. The electromechanical system is selected from the group consisting of different microelectromechanical systems on or in the microelectromechanical system layer or any combination including at least one of the foregoing control components. 20 5 · A method of manufacturing a micro-electromechanical system layer, comprising: providing a first layer including a selective bond on a second layer, the selective bond including one or more weakly bonded regions and one or more Strongly bonded area; and at least a portion of a private electrical system covered by a micro 48 553891 in or on the first layer of the weakly bonded area. 6. The method according to item 5 of the scope of patent application, further comprising separating the second layer from the first layer, and minimizing damage to the micro-electromechanical system. A method for manufacturing a micro-electromechanical system device, comprising: providing a first layer and a second layer; processing the first layer for weak bonding, the second layer falling between the first layer and the second layer A region of both; joining the first and second layers; and 10 One or more microelectromechanical systems are formed on the first layer of the weak junction area. 8. A method of manufacturing a micro-electromechanical system device, comprising: selectively attaching a first layer to a second layer; and forming one or more layers on the first layer of the weakly bonded area MEMS. ρ 9. The method of claim 8 in which the selective bonding comprises treating the interface between the first layer and the second layer with an adhesive material or a processing step to provide a strong bonding area, while going further , Wherein the weak bonding area remaining at the interface between the first layer and the second layer is not treated with an adhesive material or a processing step. 〇. The method of claim 8 in which the selective bonding includes treating the interface between the first layer and the second layer with an adhesive material or a processing step to provide a strong bonding area, while further, The weak junction area remaining at the interface between the first layer and the second layer is then processed to a lower degree than the strong junction area. 49 553891 The scope of patent application 丨 1. The method according to item 8 of the scope of patent application, wherein the selective subsequent inclusion of the interface between the first layer and the second layer provides The strong bonding area of the interface with the second layer is larger and the weak bonding area is more porous. 12. The method of claim 8 in the scope of the patent application, wherein «selective bonding is included at the interface between the first layer and the second layer to provide a weak junction area with a large number of pillars. 13. The method according to the scope of the patent application, wherein the selective bonding includes providing a weak bonding region of a porous carbon material at the interface between the first layer A and the second layer 4. 14. The method of claim 8, wherein the selective bonding is included at the interface between the first layer and the second layer to provide a weak bonding area that is lightly fired to improve adhesion. 15 15. The method according to item 8 of the patent application, wherein the selective adhering t is provided at the interface between the first layer and the second layer to have a material derived from Weakly bonded areas of porous solid materials of the composition. 16. A method as claimed in claim 8 wherein the selective bonding comprises an interface between the first layer and the second layer to provide a weakly bonded region with a -void. 17. The method as claimed in claim 8, wherein the selective subsequent step comprises providing a weak bonding region with a metal at an interface between the first layer and the second layer, wherein the first layer and the second layer The layer contains a semiconductor, an insulator, or a combination of a semiconductor and an insulator. 50 553891 Patent application scope 18. The method according to item 8 of the patent application scope, wherein the selective bonding comprises an interface between the first layer and the second layer to provide a strong bonding region with hydrophilic properties. 19. The method of claim 8 in the scope of patent application, wherein the selective bonding package 5 includes an interface between the first layer and the second layer to provide a strong bonding region with an adhesive, wherein the interface can be obtained by The light is delaminated. 20. A method as claimed in item 8 of the patent scope, wherein the selective subsequent inclusion of an interface between the first layer and the second layer provides a 10 domains of weak junctions of ions or particles. 15 20 2 ^. The method according to item 8 of the patent application, wherein the selective bonding comprises-by eutectic, fusion, anode, vacuum, van der Waals, chemical bonding, hydrophobic phenomenon, hydrophilic phenomenon, hydrogen bonding, Columbus force, capillary force, very short-range force, or a joining technique selected from the group consisting of at least one of the foregoing joining techniques. 22. The method according to item 8 of the scope of patent application, the domain 0 between the first layer and the second layer. The selective bonding package provides a strong bonding area around the interface… / 戍, and further includes scanning the strong bonding areas in a logical manner, so that the first layer consists of the second layer < 〇 51