TWI285421B - Packaging structure having connector - Google Patents

Packaging structure having connector Download PDF

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Publication number
TWI285421B
TWI285421B TW091132997A TW91132997A TWI285421B TW I285421 B TWI285421 B TW I285421B TW 091132997 A TW091132997 A TW 091132997A TW 91132997 A TW91132997 A TW 91132997A TW I285421 B TWI285421 B TW I285421B
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TW
Taiwan
Prior art keywords
substrate
connector
electrically connected
package structure
printed circuit
Prior art date
Application number
TW091132997A
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English (en)
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TW200408093A (en
Inventor
Chih-Pin Hung
Original Assignee
Advanced Semiconductor Eng
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Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW091132997A priority Critical patent/TWI285421B/zh
Priority to US10/680,209 priority patent/US6974334B2/en
Publication of TW200408093A publication Critical patent/TW200408093A/zh
Application granted granted Critical
Publication of TWI285421B publication Critical patent/TWI285421B/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/7076—Coupling devices for connection between PCB and component, e.g. display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
    • H01R12/714—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit with contacts abutting directly the printed circuit; Button contacts therefore provided on the printed circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
    • H01R12/716—Coupling device provided on the PCB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10492—Electrically connected to another device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S439/00—Electrical connectors
    • Y10S439/945—Adapter for pcb or cartridge

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

1285421 九、發明說明： 【發明所屬之技術領域】 更特別係有關 本發明係有關於一種半導體之封裝構造 於一種具有連接器之封裝構造。 【先前技術】 、半導體封裝主要具有四個功能，包括：訊號的連接、電 源的連接、熱量的散發、以及保護。一般而言，半導體晶 片係先形成-包封體(enclos叫，例如單一晶片模組(SCM) 或晶片承載器（Chipcarrier)，稱為第一階段的封裝，亦即半 導體封裝。這些封裝後的晶片，伴隨著其他的元件，諸如 電容、電阻、電桿、濾波器、開關、光學元件、及rf元件 等等，係於第二階段封裝中，組裝在—印刷電路板上。 隨著更輕更複雜電子裝£需求的日㈣，烈，晶#的速度 及複雜性相對越來越高。半導體晶片需要提供相對上更多 的接腳，用以輸入及輸出訊號。然而，習用之半導體封裝 構這諸如小外开> 封裝（Small 〇utline package ; s〇p)、四 方平坦封裝（Quad Flat Package ; QFP)、（Ball Grid Array ; BGA)’皆僅能提供單一方向的連接。若需要電性連接多方 向立體配置的電子裝置，則需要提供複雜的連接器及連接 線，用以相互電性連接兩印刷電路板，始得以電性連接該 電子裝置。 有鑑於此，便有需供一種半導體封裝構造，能夠於多個 方向上，電氣篇接至外部之印刷電路板或電子元件上。 00579-TW/ASE-432 5 1285421 【發明内容】 本發明之一目的友於W姐 勺在於k供一種具有連接 造，可於多個方向上，連接$^ ^^# 置上。 妾至外σ卩之印刷電路板或電子裝 為達上述目的，本發明蔣 ^甘# 嗌月棱供一種具有連接器之封裝構 造’其係用於電性遠接5 —玫六 ^ w "卩P刷電路板及一外部電子 裝置，其包括一基板、一半導體曰 卞守餸日日片、一封膠塑料、 該基板係電性連接至該外部印刷電路板。該ΐ ¥體4㈣置於該基板±，且純連接至該基板。該封 膠塑料包封該半導體晶片。該連接器係配置於該基板上， 用以將斜導體晶片電性連接至料部電子裝置。 综前所述，根據本發明之半導體封裝構造具有連接器， 可以提供多方向的連接。女曾 7連接尤其，該半導體封裝構造適用於 系統級封裝（System in Packwp · ς . Ρ、 , racKage , SiP)，以便能夠提供_ 體化的電子模組。 、 他目的、特徵、和優點能更明 ’並配合所附圖示，作詳細說 為了讓本發明之上述和其 顯，下文特舉本發明實施例 明如下。 【實施方式】 參考第1圖，其顯示根據本發明之第一實施例之半導體 封裝構造10。該半導體封裝構造1〇大體上係為一球袼陣 列（Ball Grid Array’· BGA)封裝構造，具有一半導體晶片12 藉由導線（Boiling Wire)14連接至基板16上，該半導體晶 片12及該導線14係為一封膠塑料18所包封。亦即，該半 00579-TW/ASE-432 6 1285421 導體晶片12係藉由打線連接（wire B〇nding)，電性連接至 該基板1 6。 該半導體封裝構造10之該基板16具有錫球（s〇lder
Ball)20，係經由導電通孔（via)(圖中未示）電性連接至該晶 片12用以電性連接至一第一外部之印刷電路板24上。 一連接器22可藉由表面黏著技術，電性連接於該基板16 上，並電性連接至該晶片丨2，用以電性連接至一外部電子 裝置，諸如一第二外部的印刷電路板（圖中未示）上。顯而 易見的，該基板16之錫球20係經由該基板16之底部連接 至忒第一外部印刷電路板，而該連接器22係經由該基板 6之頂σ卩連接至该第二外部印刷電路板。顯而易見的，該 連接器22可女裝為各種不同的方向，藉此將該該半導體封 裝構造10由該各種不同的方向連接至該第二外部印刷電 路板。 現明參考第2圖，其顯示根據本發明之第二實施例之半 導體封裝構造30。該半導體封裝構造3G大體上係為一覆 晶球格陣列（Flip_Chip Ball Gdd Array)封裝構造，具有一半 導體晶片32藉由凸塊(圖中未示)連接至基^上，以及 一封膝塑料38填充於該半導體晶片32與該基板利。亦 即，該半導體晶片3G係藉由覆晶技術，電性連接至該基板 1 6 〇 該半導體封裝構造3〇之該基板36具有錫球㈣如 BaU)4〇 ’係經由導電通孔（Via)(圖中未示）電性連接至該晶 片32,用u電性連接至一第一外部之印刷電路板⑽中未示 00579-TW/ASE-432 7 1285421 器42可藉由表面固定技術（surface Mount Tec日hnolGgy)，電性連接於該基板％之邊緣，並電性連接至 4 M片、32用以電性連接至一第二外部的印刷電路板（圖中 未示）或-外部電子裝置上。顯而易見的，該基板％之錫 球4〇係經由該基板36之底部連接至該第—外部印刷電路 板而4連接器42係經由該基板36之側面連接至該第二 外部印刷電路板。 月多考第3 4圖’其顯示根據本發明之第三實施例之 ^導體封裝構4 5〇。該半導體封裝構造5G具有兩半導體 刀別藉由凸塊60、62電性連接至一頂部基 板56及-底部基板58,且封膠塑料料、66分別填充於該 晶片52、54及該基板56、58之間。 該半導體封裝構造5〇另具有—中間基板68，藉由錫球 72電性地相互連接該頂部基板％及該底部基板μ。該中 間基板68具有大體上u字形的 子/的外形，亦即該中間基板68 具有一開口，用以容納一查技 ^ 内連接裔70。該底部基板具有錫球 (Solder Ball)67，用以電性連接δ 馇 (圖中未示）上。該連接哭70=由一锡=7部印刷電路板 υ係稭由錫球74電性連接至該 頂部基板5 6及該底部基板5 8。 精於本技藝者將可瞭解，該兩^ 52、μ 連接至該兩…、58，且該兩基板56、58係藉丄 間基板68及該錫球72相互電性連接，故該兩晶片”、“ 可電性連接至該底部基板62之錫球67，而連接至兮第一 外部印刷電路板。該連接器7〇可與一側面之第二外部印刷 00579-TW/ASE-432 8 1285421 5〇之該頂部基板 氣連接至額外的電 電路板相電氣連接。該泮導體封裝構造 56亦可提供錫球或其他的連接裝置，電 子裝置上。 精於本技藝者將可瞭解，本發明之該半導體封裝構造並 不限於圖球格陣列封裝構造，其他的封裝料 針狀格陣列（PlnGridArray;PGA)等等，亦可 器，而提供多個方向的連接。 連接 綜前所述，輯本發明之半導體封裝構造具 可以提供多方向的連接。尤其，該半導體封裝構造適用°於 糸統級封裝（System ln Paekage ; Sip)，以便體 化的電子模組。 捉仏體 雖然前述的描述及㈣已“本發明之較佳實施例，必 須瞭解到各種增添、修改和取代可能㈣於本發明較 施例’而不會脫離如所附巾請專利範圍所界定的本發 理之精神及範圍。熟悉該技藝者將可體會本 用 Γ多形式、結構、佈置、比例、㈣、元件和組件2 因此’本文於此所揭示的實施例於所有觀點，應被視 ::以說明本發明，而非用以限制本發明。本發明的範圍 應由後附申請專利範圍所界定，並涵蓋其 2 不限於先前的描述。 j寻初亚 00579-TW/ASE-432 9 1285421 【圖式簡單說明】 第1圖：係根據本發明之第一實施例之封裝構造之立體 示意圖。 第2圖：係根據本發明之第二實施例之封裝構造之立體 示意圖。 第3圖：係根據本發明之第三實施例之封裝構造之立體 示意圖。 第4圖：係第3圖中本發明之第三實施例之該封裝構造 之剖面示意圖。 00579-TW/ASE-432 10 1285421 【主要元件符號說明】 10 半導體封裝構造 12 半導體晶片 14 導線 16 基板 18 封膠塑料 20 錫球 22 連接器 24 外部之印刷電路板 30 半導體封裝構造 32 半導體晶片 36 基板 38 封膠塑料 40 錫球 42 連接器 50 半導體封裝構造 52 半導體晶只 54 半導體晶片 56 頂部基板 58 底部基板 60 凸塊 62 凸塊 64 封膠塑料 66 封膠塑料 67 錫球 68 中間基板 72 錫球 70 連接器 74 錫球 00579-TW/ASE-432 11

Claims (1)

1285421 十、申請專利範圍： 卜一種具有連接器之封裝構造，其係用於電性連接至一外 邛印刷電路板及一外部電子裝置，其包括· 一基板，電性連接至該外部印刷電路板； :半導體晶片，配置於該基板上，且電性連接至該基板； 以及 用以將該半導體晶片電性 一連接器，配置於該基板上 連接至該外部電子裝置。 2\依申請專利範圍帛1項之具有連接器之封裝構造，其中 4基板具有複數個錫球，電性連接至該半導體晶片，用 以將该半導體晶片電性連接至該外部印刷電路板。 3 \依申請專利範圍帛i項之具有連接器之封裝構造，其中 忒基板具有複數個針狀接腳（pin)，電性連接至該半導體 晶片，用以將該半導體晶片電性連接至該外部印刷電路 板0 4、依申請專利範圍帛i項之具有連接器之封裝構造，其中 該連接器係藉由表面固定技術，配置並電性連接至該基 板上。 ^ 土 、依申請專利範圍第1項之具有連接器之封裝構造，其中 該半導體晶片係藉由打線連接（Wire B_ing),電性連接 至該基板。 依申請專利範圍第1項之具有連接器之封裝構造，其中 該半導體晶片係藉由覆晶技術，電性連接至該基板。 00579-TW/ASE-432 12 1285421 ，另包 7、依申請專利範圍第丨項古 步1項之具有連接裔之封裝構造 含一封膠塑料，包封該半導體晶片。 種具有連接器之封裝槿；生 1在 丁忒稱k，其係用於電性連接至一 部印刷電路板及一外部電子裝置，其包括·· 一第一基板； 一第一半導體晶片，電性連接至該第一基板； 一第二基板； 第二半導體晶片，電性連接至該第二基板； 中間基板’用以相互電性連接該第—基板及該第二基 :連接器，電氣連接至該第一基板及該第二基板，其中 該第:基板係電氣連接至該外部印刷電路板，且該連接器 係電氣連接至該外部電子裝置。 9、依申請專利範圍第8項之具有連接器之封裝構造，盆中 該第一基板具有複數㈣球’ ^電性連接至該外部印 刷電路板。 10、 依:請專利範圍第8項之具有連接器之封裝構造，其 中該第一基板具有複數個針狀接腳（pin)，用以電性 至該外部印刷電路板。 11、 依申請專利範圍第8項之具有連接器之封裝構造，其 中。亥第及第一半導體晶片係藉由打線連接（Wire Bonding)，分別電性連接至該第一及第二基板。 12、 依申請專利範圍第8項之具有連接器之封裝構造，其 00579-TW/ASE-432 13 1285421 中該第一及第二半導：體晶片係藉由覆晶技術，分別 連接至該第一及第二基板。 1 3、依申請專利範圍第8項之具有連接器之封裝構造 包括一第一及第二封膠塑料，分別包封該第一及第 導體晶片。 電性 ，另 二半 00579-TW/ASE-432 14 1285421 七、指定代表圖： (一） 本案指定代表圖為：第（1)圖。 (二） 本代表圖之元件符號簡單說明： 10 半導體封裝構造 12 半導體晶片 14 導線 16 基板 18 封膠塑料 20 錫球 22 連接器 24 外部之印刷電路板 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式： 00579-TW/ASE-432
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7604486B2 (en) * 2006-12-21 2009-10-20 Intel Corporation Lateral force countering load mechanism for LGA sockets
TWI335070B (en) * 2007-03-23 2010-12-21 Advanced Semiconductor Eng Semiconductor package and the method of making the same
TWI473553B (zh) 2008-07-03 2015-02-11 Advanced Semiconductor Eng 晶片封裝結構
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US8012797B2 (en) * 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US8011950B2 (en) 2009-02-18 2011-09-06 Cinch Connectors, Inc. Electrical connector
US8198131B2 (en) 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
TWI408785B (zh) 2009-12-31 2013-09-11 Advanced Semiconductor Eng 半導體封裝結構
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI419283B (zh) 2010-02-10 2013-12-11 Advanced Semiconductor Eng 封裝結構
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
TWI451546B (zh) 2010-10-29 2014-09-01 Advanced Semiconductor Eng 堆疊式封裝結構、其封裝結構及封裝結構之製造方法
TWI445155B (zh) 2011-01-06 2014-07-11 Advanced Semiconductor Eng 堆疊式封裝結構及其製造方法
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
KR101434135B1 (ko) * 2014-03-17 2014-08-26 스마트전자 주식회사 퓨즈 저항기
CN113311548A (zh) * 2020-02-27 2021-08-27 华为终端有限公司 光学模组及电子设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157480A (en) * 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5808873A (en) * 1997-05-30 1998-09-15 Motorola, Inc. Electronic component assembly having an encapsulation material and method of forming the same
US6573609B2 (en) * 1997-11-25 2003-06-03 Tessera, Inc. Microelectronic component with rigid interposer
US6294731B1 (en) * 1999-03-16 2001-09-25 Performance Interconnect, Inc. Apparatus for multichip packaging
US6307749B1 (en) * 2000-10-23 2001-10-23 Delphi Technologies, Inc. Overmolded electronic module with underfilled surface-mount components
US6633490B2 (en) * 2000-12-13 2003-10-14 International Business Machines Corporation Electronic board assembly including two elementary boards each carrying connectors on an edge thereof
US6469909B2 (en) * 2001-01-09 2002-10-22 3M Innovative Properties Company MEMS package with flexible circuit interconnect

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