TWI331371B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
TWI331371B
TWI331371B TW096113749A TW96113749A TWI331371B TW I331371 B TWI331371 B TW I331371B TW 096113749 A TW096113749 A TW 096113749A TW 96113749 A TW96113749 A TW 96113749A TW I331371 B TWI331371 B TW I331371B
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Taiwan
Prior art keywords
layer
wafer
semiconductor device
metal layer
wafers
Prior art date
Application number
TW096113749A
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English (en)
Other versions
TW200843000A (en
Inventor
Chin Huang Chang
Chien Ping Huang
Chih Ming Huang
Cheng Hsu Hsiao
Cheng Chia Chiang
Original Assignee
Siliconware Precision Industries Co Ltd
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Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW096113749A priority Critical patent/TWI331371B/zh
Priority to US12/105,538 priority patent/US20080258306A1/en
Publication of TW200843000A publication Critical patent/TW200843000A/zh
Application granted granted Critical
Publication of TWI331371B publication Critical patent/TWI331371B/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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1331371 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置及其製法，尤指一種 可供垂直堆疊之半導體裝置及其製法。 【先前技術】 由於通訊、網路、及電腦等各式可攜式（P〇rtable) 電子產品及其周邊產品輕薄短小之趨勢的日益重要，且該 等電子產品係朝多功能及高性能的方向發展，以滿足半導 _體封裝件高積集度（Integration)及微型化 (Miniaturization)的封裝需求，且為求提昇單一半導體 封4件之性能（abi 1 ity)與容量（capacity)以符合電子產 品小型化、大容量與高速化之趨勢，習知係以半導體封裝 件多晶片模組化（Multichip Module ; MCM)的形式呈現， 以在單一封裝件之基板（如基板或導線架）上接置至少二 個以上之晶片。 鲁 凊參閱第1圖，即顯示一習知以水平間隔方式排列之 夕μ片半導體封裝件。如圖所示，此半導體封裝件包含有 基板100，一第一晶片11〇，具有相對之主動面 和非主動面110b，且其非主動面ii0b係黏接至該基板1〇〇 上，並以第一導線120將該第一晶片11〇之主動面11〇& 電性連接至該基板1 〇〇 ;以及一第二晶片丨40，具有相對 之主動面140a和非主動面140b，其非主動面14〇b係黏 接至該基板100並與該第一晶片間隔一定之距離，再以第 一 ‘線150將§亥苐一晶片140之主動面i4〇a電性連接至 110276 6 1331371 該基板100。 上述習知多晶片半導體封裝件之主要缺點在於為避 免BB片間之導線誤觸，須以一定之間隔來黏接各該晶片， •故若需黏接多數之晶片則需於基板上佈設大面積的晶片 .接置區域（Die Attachment Area)以容設所需數量之晶 片，此舉將造成成本之增加及無法滿足輕薄短小之需求。 復請參閱第2圖，係顯示習知如美國專利第 6, 538, 331號案所揭露以疊晶方式（Stacked)將第一晶片 # 210及第二晶片240疊接於基板200上，同時各該疊接晶 片係相對下層晶片偏位（off_set) —段距離，以方便該第 一及第二晶21 0,240分別打設銲線22〇25〇至該基板 200。 此方法雖可較前述以水平間隔方式排列多晶片之技 術節省基板空間，惟其仍須利用銲線技術電性連接晶片及 基板’使晶片與基板間電性連接品質易受銲線之線長影響 而導致电性不佳，同時由於該些晶片於堆 鲁㈣，且加上銲線設置”之料，㈣可能造成晶片堆 豐面積過大而無法容納更多晶片。 為此，美國專利此6,642,〇81、5,270,261及 6,809,421揭露-種利用妙貫通電極（ThrQUgh siiic〇n
Via, TSV)技術以供複數半導體晶片得以垂直堆疊且相互 電性連接。惟其製程過於複雜且成本過高，因此欠缺產業 實用價值。 另外’美國專利第5,71 6,759、6,〇4〇,235、 110276 7 1331371 5, 455, 455、6, 646, 289、6, 777, 767 等則揭露一種相對 上、下表面設有導電線路之晶片，其係自包含有複數晶片 之晶圓非主動面形成切割槽口，並利用濺鍍（sputtering) 技術以線路重配置層（Redistribution Layer，RDL)方式 .形成晶片主動面銲墊至非主動面之電性導通，惟其由於係 自該晶圓非主動面（背面）形成切割槽口關係，故不易對正 至正確位置，造成後續線路位置偏差無法正確及有效電性 ‘連接晶片主動面及非主動面，甚至毀損到晶片；此外，因 #該製程中多次使用線路重配置層（Redistributi〇n。”厂 RDL)技術，導致製程成本增加及複雜度提高丨再者，因該 製程係直接於-晶圓上進行，因此並未考量晶片不良品問 題:如此將導致即便該晶圓中具有不良品晶片，仍須持續 進行製程，造成材料浪費及成本增加問題。 貝 是以，如何解決上述習知半導體裝置問題，並開發一 種不增加面積而可有效在封裝件中整合更多晶片以提x升 電性功能，同時避免使用銲線技術所導致電性不佳， 使时貫通電極（TSV)及多次使㈣鍍技程 =雜且成本過高’以及直接於晶圓上進行製程二= 曰曰片良品等《題，實為目前亟欲解決的課題。 【發明内容】 提供所述先前技術之缺點，本發明之-目的在於 封袭件中整合更多之晶片。 積下，於 本發明之另一目的在於提供一種半導體褒置及其製 J10276 8 1331371 較簡便之方式進行製程，避免多次使用賴作 業所導致製程過於複雜且成本過高問題。 ，月之再目的在於提供-種半導體裝置及直製 用vr供複數半導體晶片垂直堆4且電性連接，避免使 用龄線技術所導致電性不佳問題。 本發明、，另了目的在於提供一種半導體裝置及其製 用矽導體晶片垂直堆疊且電性連接，避免使 用夕貝通黾極（TSV)導致制炉，A> , ,^ 致衣輊過於稷雜且成本過高問題。 之又目的在於提供一種半導體裝置及製 法’可確保所使用之晶片為良品晶片。 /、 本發明之復一目的在於提一 之半導體裝置及其製法。 #低成本且製程簡易 t月之A目的在於提供-種半導體裝置及I掣 題1免於晶圓背面形成切割槽口所易造成毁損晶片、問 制法Ί上f及其他目的，本發明揭露一種半導體裝置之 係包括：提供-具有複數晶片之晶圓，該晶片及曰 圓具有相對之主動面及非主動面，夂該曰 2曰曰 複數銲塾，經測試(cp)確認各該晶片良：後，於相 相互電性連接之第-金屬層;薄化心圓 t動面’並貼附於一膠片上以沿各該晶片間進行切判而 7各以片4該些確定為良好晶片之晶片以相 t間隙方式接置於一表面設有複數導電線路之承载板 上’以使該晶片覆蓋該導電線路之-端，且令該導電 110276 9 -顯露於該晶片間隙；於誃曰片門险士 士 ,應各晶片周圍之介電；”七、充一介電層，並對 路部分；於該此曰曰片及曰=口，以外露出該導電線 β二日日片及介電層上覆# 一 、 •形成有開Π以外露出各节晶片二二層，則吏該阻層 ‘口部分；於該介電芦金屬層至介電層開 層，以供㈣曰二:：層開口中形成第二金屬 •電性連接至“夕過该第一金屬層及第二金屬層而 %丧主省¥電線路；移除該阻層，並 s ‘；丨電層進行切割及移 σ Μ二日曰片間之 籲使該導1攸a 载1^以分離各該晶片，並 導體裝ϋ 路於該晶片非主動面’以構成本發明之半 將—半導體裝置彻其W非主動 疊並電性連接至另-半導體裝置主動面 金屬層，藉以構成多晶片之堆疊結構。 (二，晶片為已經確認之良好晶片 載板上r 片透過一接著層而接置於該承 板上。该弟一金屬層係利用線路重配置層 上對廊ΐΓΓΐοη Laye:’RDL)技術而形成該晶圓主動面 进…目鄰晶片間’藉以電性連接相鄰晶片之鮮塾。該 八載板係為金屬板，以透過電鍍方式於該介電層開= =開口中形成電性連接該晶片第一金屬層與導電線路" 以二金屬層，進而使該晶片主動面上之銲塾得以透過該 弟:金屬層、第二金屬層而電性連接至該晶片非主動面上 之導电線路，該第二金屬層係包括銅/鎳/銲錫材料。 另外復可於形成第二金屬層並移去阻層後，於該晶圓 110276 10 1331371 主動面及該金屬層上覆蓋—絕緣層，接著將該承載板移 除，以形成-薄型之晶片尺寸半導體裂置_
Package，CSP)。再者，可於該晶片非主動面上之導電線 路植設導電元件，以供後續利用該導電元件電性連接：’外 部裝置或直接進行半導體裝置間之堆疊。 再者，於利用線路重配置層⑽L)技術形成第 #時，亦可使該第—金屬層通過該銲塾而朝向晶片中心延 :分佈’並於該第一金屬層延伸部分終端形成有延神墊， ^此即可供後續於該延伸墊上堆疊、接置不同之電子元 括曰透過前述曰製法’本發明復揭露一種半導體裝置，係包 曰曰片、亥曰曰片具有相對之主動面及非主動面，且唁主 動面上设有複數個銲墊，於該 第—全凰庳·道布 主工芏主動面邊緣形成有 電層係形成於該晶片非主動面上；介 曰’、復皿於5亥晶片側邊，且該介電層中刑# # 顯露出該導電線路部分;以及第二全;：中：成有開口以 i屬層上，以供晶片銲墊透過該第一及第 --屬層電性連接至導電線 f 該導電線路間復弗占古拉—a "亥阳片非主動面與 該接著層邊緣者層，且該導電線路係相對設於 二金置復包括有覆蓋於該晶片主動面及該第 電材料，以形及日植^於該導電線路外表面之導 亦v 4型之晶片尺寸半導體襄置（csp)。 ，本發明之半導體裝置及其製法，主要係提供 110276 11 1331371 一表面設有複數導電線路之承 設有電性連接至銲塾之第—金屬=於主動面邊緣 接置於該承載板上並覆蓋該導電‘：二以將該些晶片 •路相對顯露於該些晶片間隙，農中、此曰一"而，且使導電線 •好晶片，避免習知直接於晶圓晶片係已雄認為良 良品問題所造成材料浪費及仃衣程而未考量晶片不 片間隙中填充一介帝声，二斜虛曰加問題’接著於該些晶 複數開口，以外露：該Ί二晶片周圍之介電層形成 I電層表面覆蓋-阻層，並使^阻:分，且於該些晶片及介 該晶片銲塾上第-金屬層至:;電=成有/1口以外露出各 方式於該介電層開口及該阻層開 亥：“塾透過該第—及第二金屬層 4路，避免習知多次使用減鍍製程所 二 且成本過高問題，之後移除該阻層 〔日複雜 •該導電線路外露於該晶=動:==，並使 ，程序形成本發明之半導體裝置。U透過低成本及簡易 上之一該半導體裝置以外露於晶片非主動面 半^ ^ 電性連接至W承載件上，並將另一 ^導體裝置利用外露於晶片非主動面上之導電㈣^ :電性連接至先前之該半導體裝置中晶月主動面上之第 :^層’藉以構成多晶片之堆疊結構，俾可在不增 ^積情況下進行垂直堆疊，以有效整合更多晶片、提升 力月b，同恰避免使用銲線技術所導致電性不佳及使用 】10276 ]2 1331371 矽貫通電極（TSV)所造成製程複雜及成本高等問題。 【實施方式】 以下係藉由特定的具體實施例說明本創作之實施方 式，所屬技術領域中具有通常知識者可由本說明書所揭示 •之内容輕易地瞭解本創作之其他優點與功效。 第一實施例 • 請參閱第3A至3G圖，係為本發明之半導體裝置及其 . 製法第一實施例之示意圖。 φ 如第3A及3B圖所示，提供一具有複數晶片30之晶 圓300，該晶片30及晶圓300具有相對之主動面30a及 非主動面30b，各該晶片主動面上設有複數銲墊301，經 測試（CP)確認各該晶片良窳後，利用線路重配置層（RDL) 技術以在相鄰晶片之鮮塾間形成有相互電性連接之第'— 金屬層3 0 2。該第一金屬層3 0 2例如為銲塊底部金屬層 (UBM)，其材質可為鈦/銅/鎳（Ti/Cu/Ni)、鈦化鎢/金 (TiW/Au)、铭/鎳化鈒/銅（Al/NiV/Cu)、鈦/鎳化鈒/銅 鲁（Ti/NiV/Cu)、鈦化鎢/鎳（TiW/Ni)、鈦/銅/銅 (Ti/Cu/Cu)、鈦/銅/銅/鎳（Ti/Cu/Cu/Ni)等。 接著薄化該晶圓非主動面至25-100 μ m，以將該晶圓 藉其非主動面接置於膠片32上，再沿各該晶片30間進行 切割而分離各該晶片30，以將良好之晶片30(Good Die) 取出。 如第3C圖所示，將良好之晶片30以其非主動面並間 隔一接著層34而與該承載板31相接合，其中該些晶片 13 ]10276 !331371 30相互間留有間隙3〇3,以覆蓋該導電線路仙之一端， ^吏該導電線路310相對顯露於該些晶片間隙3()3。該接 考層34之材質例如為β階段（B_stage)的環氧樹脂 (epoxy)。 該承載板31例如為銅材質之金屬板，以透過電鍍方 .式於其表面形成複數導電線路31〇，該導電線路31〇係例 如為金/鎳/金（Au/Ni/Au)，其厚度約〇.5_3^^。
. 如第3D及3D，圖所示，其中該第3D，圖係為對庳第3D •圖局部放大圖，於該些晶片3〇之間隙3〇3中填充二^ 乳樹脂（Epoxy)或聚亞醯胺（p〇lyimide)之介電層35，並 對應各晶片30周圍之介電層35利用雷射或蝕刻等方式形 成複數開口 350 ’以外露出該導電線路31〇部分。該介電 2開口 350與晶片30側邊保持一間隔，以使介電層犯电 覆蓋於該晶片30侧邊，其中該覆蓋於晶片側邊之介電層 35主要係供後續形成之金屬層之絕緣用。 φ 如第3E圖所示，於該些晶片30及介電層35上覆蓋 如軋膜（Dry-fil"〇之阻層36，並使該阻層36形成有開 口 360以外露出各該晶片3〇上第一金屬層3〇2至介電層# 開口 350部分。 曰 如第3F圖所示，利用該金屬材質之承載板31及其上 之導電線路310，以透過電鍍方式而於該介電層開口 35〇 及該阻層開口 360中沈積第二金屬層37，以供各該晶片 銲墊301透過該第一金屬層3〇2及第二金屬層3?而^性 連接至該導電線路310。該第二金屬層37包含鋼 Π0276 14 1331371 鎳（Ni)372/銲錫（s〇ider)373，其係先沈積銅371於該介 電層開〇 350中，並覆蓋該介電層3〇及晶片主動面上之 第至屬層302後，再持續於該銅371上沈積錦372及録 .錫 373 。 如第3G圖所示，移除該阻層36 ’並沿該些晶片3〇 =之介電層35進行㈣及利用如㈣方式移除該金屬材 質之承載板31，藉以分離各該晶片3〇，並使 310外露於該晶片3〇非主動面，以構成本發明之導 φ裝置。 苛版 透過前述製法，本發明復揭露一種半導體裝置，係包 括有.曰曰片30，該晶片具有相對之主動面及非主動面， 且°亥主動面上設有複數個銲墊301，於該銲墊3〇1上至主 動面邊緣形成有第-金屬層3〇2 ;導電線路31〇，係形成 ^該晶片非主動面上；介電層35，係覆蓋於該晶片加側 ’且该介電層35中形成有開σ 35G以顯露出該導電線 * h ’以及第—金屬層37 ’係形成於該介電層開 :及第-金屬層3G2上，以供晶片銲㈣透過該第一及 弟-金屬層302, 37電性連接至導電線路31〇。另外，嗜 =片30非主動面與該導電線路川間復形成有接著層 3[且該導電線路310係相對設於該接㈣％邊緣。 3參閱第4圖，後續即可將前述至少二半導體裝置 仃垂直堆豐，以利用熱壓合⑽而】c。喂咖】⑻方 :的二裝置中晶片3〇主動面之第二金屬層37 中的1 于錫材料熱炫於另-半導體裝置中晶片30非主動面 110276 15 上導電線路310，藉以構成 可於該堆疊結構中兩半導^隹豐結構。另外，亦 (_如⑴则（未圖覆晶底部填膠 強化该彼此之接合性。 請參閱第5A及5R同& &丄 製法第發明之半導體裝置及其 Λ把例之不思圖。同時為 中對應前述相同或相似之 Ώ 丁本貝％例 L咕 以之兀件係採用相同標號表示。 乂、十…5A圖所不’本實施例之半導體裝置及其製法企 :;述::例大致相同，主要差異在於形成第二金屬層、 、★去阻層後’於該些晶片⑽主動面及該第二金屬 :脂-上。1蓋,絕緣層38，該絕緣層38之材質係如環氧 片；：者再赭由蝕刻方式將承載板移除’及沿該些晶 二間隙之介電層35進行切割以分離各該晶片，以形㈣ ^•之晶片尺寸半導體裝置（csp)。 如帛5B圖所示’另可於該晶片3〇非主動面上之導電 带路31G植設如銲球之導電元件⑽，以供後續利用該導 氧元件3 9電性連接至外部裝置。 復請參閱第6圖，亦或可將前述之一半導體裝置上之 絕緣層38形成有外露該第二金屬層37之開口 38〇，且利 用另一半導體裝置中植設於導電線路31〇上之導電元件 39電性連接至外露於絕緣層開口 38()之第二金屬層π ^，以形成半導體裝置之堆疊結構（package⑽⑽哪）。 實施例 凊芩閱第7A至7E圖’係為本發明之半導體裝置及其 110276 16 1331371 製法第三實施例之示意圖。同時為簡化本圖示，本實施例 中對應前述相同或相似之元件係採用相同標號表示。 如第7A圖所*，本實施例之半導體農置法盘 •前述實施例大致相同，主要差異在於利用線路重配置層、 技術形成晶片30主動面上之第一金屬層3〇2時，曰使 該第一金屬層302通過該銲塾3〇1而朝向晶片％中心延 伸分佈’並於該第一金屬層30延伸部分終端形成有 墊 304。 如第7B圖所示，其後之製程即相類於前述實施例中 所述，將該些晶片30以相互間留有間隙3〇3方式接置於 表面設有複數導電線路310之承載板31上，以㈣ 30覆蓋該導電線路31 〇之一妓，n人 ^ 露於該晶片間隙303。 且々該導電線路⑽顯 如第礼圖所示，於該些^ 3() 35,並對應W周圍之介μ 35 ^層 350,以外露出該導電線路31〇部分。 复數開 接著於該些晶片30及介電層3 並使該阻層36形成有開D 復I P層《36 -金屬層3。2至介電二D3 ：°卜露出各該晶片3。上第 ,^ 兒層開口 350部分及該延伸墊304。 如弟7D圖所示，於該介 層開口 360之第一金屬；"口 350及外露出該阻 含有銅371/錄372/“ 37m_4上形成例如包 該晶片銲塾3G1透過該第 —^屬層3〇7，以供各 而電性連接至咳導^々 層302及第二金屬層37 連接至〜線路310,同時於該晶片主動面第一 110276 17 1331371 金屬層302终端之延伸墊3〇4上形成有第二金屬層打。 之後即可移除該阻層。 曰 如第7E圖所示，沿該些晶片3〇間之介電層託進行 切割及移除該承載板31，藉以分離各該晶片30，並使兮 之半導體I置非動面，以構成本發明 .復二⑽8圖，於該晶月3。主動面及該第二金屬 .曰 ’丁、可覆盍一絕緣層38，該絕緣層38對應嗲延仲 φ墊304位置處形成有開口 3 瓿…<1伸 乂外路出该延伸墊304上之 :罢屬層37’俾供後續於該延伸墊之第二金屬 導電線路則植設如鲜球之導電t 主動面上之 兮道+ - 毛兀件39，以供後續利用 该導電兀件39電性連接至外部裝置。 交只㈣ 因此，本發明之半導體裝置制 表面設有複數導雨峻踗β I 4八衣 要係提供一 Ϊ 载板及複數於主動面邊緣咬 有电性連接至銲塾之第一金屬層之 邊I又 置於該承載板上並覆蓋該導電線路之—端，片接 相對顯露於該些晶片間隙，其中該些 ^線路 晶片，避免習知直接於晶圓上進行製::認為良好 品問題所造成材料浪費及成本增二王 量晶片不良 間隙中填充一介電層，並對應各晶片^圍=於該些晶片 數開口，以外露出該導電線路部八 1 電層形成複 層表面覆蓋一阻層，並使該阻層升^ 7些晶片及介電 晶片銲塾上第一金屬層至介汗口以外露出各該 層開口部分’再利用電錢方 110276 18 1331371 式於該介電層開口及該阻層開口中形成第二金屬層，以供 該晶片銲墊透過該第一及第二金屬層電性連接至^導命” 線路’避免習知多次使用雜製程所導致製程過於複雜"且 •成本過高問題’之後移除該阻層，並沿該些晶片間之^電 •層進行切割及移除該承載板，藉以分離各該晶片，並: 導电線路外露於該晶片非主動面，以透過低成本及簡易程 •序形成本發明之半導體裝置。後續，即可將一該半導體裝 .置：外露於晶片非主動面上之導電線路接置並電性連接、 ⑩至晶片承載件上’並將另—半導體裳置利用外露於晶片非 主動面上之導電線路接置並電性連接至先前之該半導體 裝置中晶片主動面上之第二金屬層，藉以構成多晶片之堆 豐結構，俾可在不增加堆疊面積情況下進行垂直堆疊以 〜文正口更夕日日片、提升電性功能，同時避免使用銲線技 价所‘致毛性不佳及使用石夕貫通電極所造成製裎複 雜及成本高等問題。 _ 以上所述之具體貫施例，僅係用以例釋本發明之特點 •及功效，而非用以限定本發明之可實施範田壽，在未脫離本 ^月^揭之精神與技術範_下，任何運用本發明所揭示内 而70成之等效改變及修飾，均仍應為下述之申請專利範 圍所涵蓋。 【圖式簡單說明】 第1圖係為習知以水平間隔方式排列之多晶片半導 體封裝件剖面示意圖； f 2圖係為美國專利第6, 538, 331號案所揭示之以叠 110276 1331371 ,日曰（Sl:acked)方式進行多晶片堆疊之半導體封裝件剖面 示意圖； _ 第3A至3G圖係為本發明之半導體裝置及其製法第一 •實施例之剖面示意圖； 第3D圖係為對應第3D圖局部放大圖； 第4圖係為本發明第一實施例之半導體裝置堆疊示 • 意圖； - 第5Α&5β圖係為本發明之半導體裝置及其製法第二 籲實施例之剖面示意圖； 第6圖係為本發明第二實施例之半導體裝置堆疊示 意圖； ^ 第7 Α至7Ε圖係為本發明之半導體裝置及其製法第三 實施例之示意圖；以及 第8圖係為本發明第三實施例之半導體裝置堆疊電 子元件之示意圖。 【主要元件符號說明】 • 1Q 0基板 110 第一晶片 110a 主動面 110b 非主動面 120 銲線 140 第二晶片 140 a 主動面 140b 非主動面 Π0276 20 銲線 基板 第一晶片 銲線 第二晶片 銲線 晶片 主動面 非主動面 晶圓 銲墊 第一金屬層 間隙 延伸墊 承載板 導電線路 膠片 接著層 介電層 介電層開口 阻層 阻層開口 第二金屬層 銅 21 110276 1331371 372 鎳 373 銲錫 38 絕緣層 380 絕緣層開口 39 導電元件 40 電子元件

Claims (1)

1331371 十、申請專利範圍： 1.. 一種半導體裝置之製法，係包括： 提供-具有複數晶片之晶圓，該晶片及晶圓具有 相對之主動面及非主動面，各該晶片主動面上設有複 數銲墊，經測試（CP)確認各該晶片良窥後，於相鄰晶 片之銲墊間形成有相互電性連接之第一金屬層； 沿各該晶片間進行切割而分離各該晶片，以將該 些晶片以相互間留有間隙方式接置於一表面設有複^ 數導電線路之承餘上，並使該晶片覆蓋該導電線路 之一端，且令該導電線路顯露於該晶片間隙； 於該晶片間隙中填充一介電層，並對應各晶片周 圍之介電層形成複數開口，以外露出該導電線路部 於戎些晶片及介電層上覆蓋 一 — 一 /日 里Ί丈砀阻廣 V成有開口以外露出各該晶片上第一金屬層至介電 層開口部分； 於該介電層開口及該阻層開口中形成第二金屬 ^ ’以供各該晶片科透過該第—金屬層及第二金 运而電性連接至該導電線路；以及 移除該阻層，並沿該些晶片間之介電層進行 移除該承載板，II以分離各該W D 路外露於竽曰Η韭士 4 反/命包線 置。备方、痃曰曰片非主動面，以構成本發明之半導體裝 士申请專利範圍第1項之半導體裝置之製法，其中， Π0276 23 U31371 板為金屬板，以透過電鍍方式於其表面形成複 ‘二線路，1玄導電線路為金/鎳/金（Au/Ni/Au)。 二2 %專利範圍第1項之半導體裝置之製法，其中， °亥第金屬層係利用線路重配置層⑽L)技術以在晶 |員"j 十重力 ~r* | 、 囟上形成銲塊底部金屬層（UBM)，藉以電性連 接相夕#曰曰片之銲墊，且該晶圓係經薄化及該切割之晶 二、二隹„心為良好之晶片（G〇〇d Di e)，以供接於 載板上。 ' 4· 請專利範圍第1項之半導體裝置之製法，其中， ^曰日片係間隔一接著層而與該承載板相接合。 5·如1請專利範圍第1項之半導體裝置之製法，其中， ==層為環氧樹脂（EpQxy)及聚㈣胺（⑽㈤心) 之>、中一者’該阻層為乾膜。 6. 7. 8. f:請專利範圍第1項之半導體裝置之製法，其中， °玄M片周圍之介電層係利用雷射及钱刻之其中一方 式形成複數開π ’以外露出該導電線 電層開口盥晶只也卜臭奴4士 β日 ^ 兮曰Η二邊隔，以使介電層覆蓋於 “片侧邊而供後續形成之金屬層之絕緣用。 如申請專利範圍第1項之半導體裝置之製法，其中， 該第二金屬層包含銅(㈤/鎳⑻)/銲錫(S〇lder) ’係利用金屬材質之承載板，以透過電財式而先 沈和、銅於該介電層開口中，並彳Ϊ蓋該介電層及第一金 屬層後，再持續於該銅上沈積鎳及鲜錫。 如申請專利範圍第1項之半導體U之製法，其中， 110276 24 1331371 透過熱壓合（thermal compressi〇n)方式，以使 導體裝置中晶片主動面之第二金屬 一半導體裝置中晶片非主動面上 連要、另 多晶片之堆疊結構。电線路，錯以構成 9· 如申請專利範圍第8項之半導體褒置之製法，宜中， 該堆疊結射兩半導體裝置_復填充有覆晶底部 填膠（underf i 11)材料。 _ ° 10.如申請專利範圍第i項之半導體裝置之製法，其 ==二金屬層並移去阻層後’復於該些晶片、主動 及；屬層上覆蓋一絕緣詹，再移除該承載板 隙之介電層進行切割，以分離各該晶 u.如中請專利範圍第1G項之半導體裝置之製法4中， 非動面上之導電線路外表面植設有導電元件。 、如申請專利範圍第以之半導體裝置之製法，其中， 丨：邑雇層形成有外露該第二金屬層之開口，以供另一 1導體裝置中植設於導電線路上之導電元件電性連 至外露於該絕緣層開口之第二金屬層上。 13. 申請專利範圍第1項之半導體裝置之製法，其令， 〜弟:金屬層通過該銲墊而朝向晶片中心延伸分 二並於該第一金屬層延伸部分終端形成有延伸墊。 申請專利範圍第13項之半導體裝置之製法，其中， Γΐ i U相互間留有間隙方式接置於表面設有複 ν毛線路之承載板上，以於該些晶片間隙中填充介 II0276 25 1331371 電層，並對應各晶片周圍之介電層形成複數開口，再 於該些晶片及介電層上覆蓋—阻層，且使該阻層形成 有開口以外露出各該晶片上第—金屬層至介電層開 Z部分及該延伸墊，以於該介電層開口及外露出該胆 層開Π之第-金屬層及延伸塾上形成第：金屬層。 .如申請專利範圍第斤u項之半導體聚置之製法，苴令， 面及該第二金屬層上覆蓋-絕緣層:、該絕 =對應該延㈣位置處形成有開口料露出該延 接置弟一金屬層，俾於該延伸墊之第二金屬層上 設導電元件。…亥曰曰片非主動面上之導電線路植 16· —種半導體裝置，係包括： 音亥主二片：該ί片具有相對之主動面及非主動面，且 動面上设有複數個銲墊，於 緣形成有第一金屬層； ^上至主動面邊 導電線路，係形成於該晶片非主動面上； 介電層，係覆蓋於B y九，Α 成有開口以Ρ山 邊，且該介電層中形 片以頌路出該導電線路部分；以及 層上第二:2成於該介電層開。及第-金屬 接至導電線I料過該第-及第二金屬層電性連 Ή專利範圍第16項之半導雜裝置，其中，該晶 h主動面與該導電線 電線路传相设形成有接著層，且該導 係相對设於該接著層邊緣。 110276 26 ^31371 18·如申請專利範圍第16項之半導體裝置，其中，該導 電線路為金/鎳/金（Au/Ni/Au)，該介電層為環氧樹脂 (Epoxy)及聚亞酸胺（p〇iy丨以心）之其中一者，該第一 金屬層包含銅（Cu)/鎳（Ni)/銲錫（Solder)，該銅先沈 積於介電層開口中，並覆蓋該介電層及第一金屬層， 再於該銅上沈積鎳及銲錫。 -I9.如申請專利範圍第16項之半導體裝置，其中，該介 毛層開口與晶片側邊保持一間隔，以使介電層覆蓋於 • 該晶片側邊’而供第二金屬層之絕緣用。 20.如申請專利範圍第丨6項之半導體裝置，其中，該半 導體裝置中晶片主動面之第二金屬層係透過熱壓合 (thermal compressi〇n)方式而電性連接於另—半導 體裝置巾晶片非主動面上導電線路，#以構成多 之堆g結構。 21. t申請專利範圍第20項之半導體裝置，其中，該堆 疊結構中兩半導體裝置間隙復填充有覆晶底部^ (underfill)材料。 … 22·如申請專利範圍第16項之半導體裴置，復包括有絕 緣層，係形成於該晶片主動面及該第二金屬層上、” 23.如申請專利範圍第22項之半導體裝置，復包曰括有導 1元件’係植設於該晶片非主動面上之導電線路外表 24.如申請專利範圍第23項之半導體裝置，其中，’π 緣層形成有外露該第二金屬層之開口，以供另：半巴導 110276 27 1331371 體裝置中植設於導電線路上之導電元件電性連接至 外露於該絕緣層開口之第二金屬層上。 25.如申請專利範圍第16項之半導體裝置，其中，該第 一金屬層為利用線路重配置層（RDL)技術所形成之銲 塊底部金屬層（UBM)，且該晶片係經薄化及經確認為 良好之晶片（Good Die)。 .26.如申請專利範圍第16項之半導體裝置，其中，該第 - 二金屬層通過該銲墊而朝向晶片中心延伸分佈，並於 _ 該第一金屬層延伸部分終端形成有延伸墊。 27. 如申請專利範圍第26項之半導體裝置，苴中，兮延 伸墊上形成有第二金屬層。 28. 如申請專利範圍第27項之半導體裝置，i中，气晶 ^動面及該第二金屬層上覆蓋—絕緣層，該絕緣層 對應該延伸塾位置處形成有開口以外露出該延伸塾 亡：弟：金屬層’俾於該延伸墊之第二金屬層上接置 、=子τΜ牛’且於該晶片非主動面上之導電線路植設導 • 電7L件。 110276 28
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