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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.2k 621

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.4k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.5k 230

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 336

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 866 228

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 740 180

Repositories

Showing 10 of 110 repositories
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 263 Apache-2.0 34 19 40 Updated Apr 7, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 37 LGPL-3.0 655 0 0 Updated Apr 7, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    276 Apache-2.0 40 43 7 Updated Apr 7, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 6 3 0 0 Updated Apr 7, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 4,229 Apache-2.0 621 329 (1 issue needs help) 161 Updated Apr 7, 2025
  • caliptra-mcu-sw Public

    Caliptra MCU Software

    chipsalliance/caliptra-mcu-sw’s past year of commit activity
    Rust 13 Apache-2.0 2 13 4 Updated Apr 6, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 87 Apache-2.0 47 94 10 Updated Apr 6, 2025
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec’s past year of commit activity
    TeX 53 30 25 19 Updated Apr 6, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 109 Apache-2.0 53 130 58 Updated Apr 5, 2025
  • chisel-nix Public

    Nix template for the chisel-based industrial designing flows.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 38 5 2 1 Updated Apr 5, 2025

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