AT333895B - Schaltungsanordnung mit zwei miteinander verknupften schaltkreissystemen - Google Patents

Schaltungsanordnung mit zwei miteinander verknupften schaltkreissystemen

Info

Publication number
AT333895B
AT333895B AT697674A AT697674A AT333895B AT 333895 B AT333895 B AT 333895B AT 697674 A AT697674 A AT 697674A AT 697674 A AT697674 A AT 697674A AT 333895 B AT333895 B AT 333895B
Authority
AT
Austria
Prior art keywords
circuit
systems
arrangement
circuit arrangement
connected circuit
Prior art date
Application number
AT697674A
Other languages
English (en)
Other versions
ATA697674A (de
Inventor
Walter Dipl Ing Droscher
Werner Meier
Kurt Dipl Ing Winter
Original Assignee
Siemens Ag Oesterreich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag Oesterreich filed Critical Siemens Ag Oesterreich
Publication of ATA697674A publication Critical patent/ATA697674A/de
Application granted granted Critical
Publication of AT333895B publication Critical patent/AT333895B/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Control Of Electrical Variables (AREA)
  • Dc Digital Transmission (AREA)
AT697674A 1974-04-08 1974-08-29 Schaltungsanordnung mit zwei miteinander verknupften schaltkreissystemen AT333895B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2417054A DE2417054C3 (de) 1974-04-08 1974-04-08 Schaltungsanordnung mit zwei miteinander verknüpften Schaltkreissystemen

Publications (2)

Publication Number Publication Date
ATA697674A ATA697674A (de) 1976-04-15
AT333895B true AT333895B (de) 1976-12-10

Family

ID=5912472

Family Applications (1)

Application Number Title Priority Date Filing Date
AT697674A AT333895B (de) 1974-04-08 1974-08-29 Schaltungsanordnung mit zwei miteinander verknupften schaltkreissystemen

Country Status (12)

Country Link
US (1) US4032800A (de)
JP (1) JPS5542782B2 (de)
AT (1) AT333895B (de)
BE (1) BE827555A (de)
CA (1) CA1027643A (de)
CH (1) CH585486A5 (de)
DE (1) DE2417054C3 (de)
FR (1) FR2328325A1 (de)
GB (1) GB1503698A (de)
IT (1) IT1034869B (de)
NL (1) NL7501768A (de)
SE (1) SE399349B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209713A (en) * 1975-07-18 1980-06-24 Tokyo Shibaura Electric Co., Ltd. Semiconductor integrated circuit device in which difficulties caused by parasitic transistors are eliminated
JPS52121729A (en) * 1976-04-05 1977-10-13 Omron Tateisi Electronics Co Power circuit
JPS52122062A (en) * 1976-04-05 1977-10-13 Omron Tateisi Electronics Co Interface circuit
US4096398A (en) * 1977-02-23 1978-06-20 National Semiconductor Corporation MOS output buffer circuit with feedback
JPS5856531A (ja) * 1981-09-30 1983-04-04 Toshiba Corp 論理回路
CA1192634A (en) * 1982-02-26 1985-08-27 David E. Dodds Coupling an electrical signal to transmission lines
CA1197641A (en) * 1983-08-26 1985-12-03 David E. Dodds Telephone line interface circuit
JPS60157332A (ja) * 1984-12-10 1985-08-17 Nec Corp Ｃｍｏｓインバ−タ回路
US4786826A (en) * 1986-02-19 1988-11-22 International Rectifier Corporation Power interface circuit with control chip powered from power chip
JPS6350209A (ja) * 1986-08-20 1988-03-03 Matsushita Electric Ind Co Ltd レベルシフト回路
US4894562A (en) * 1988-10-03 1990-01-16 International Business Machines Corporation Current switch logic circuit with controlled output signal levels
WO1991002408A1 (en) * 1989-07-28 1991-02-21 Dallas Semiconductor Corporation Line-powered integrated circuit transceiver
US5032742A (en) * 1989-07-28 1991-07-16 Dallas Semiconductor Corporation ESD circuit for input which exceeds power supplies in normal operation
FR2676870B1 (fr) * 1991-05-24 1994-12-23 Sgs Thomson Microelectronics Structure de protection dans un circuit cmos contre le verrouillage.
US5970255A (en) * 1995-10-16 1999-10-19 Altera Corporation System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly
US6836151B1 (en) 1999-03-24 2004-12-28 Altera Corporation I/O cell configuration for multiple I/O standards
US6271679B1 (en) 1999-03-24 2001-08-07 Altera Corporation I/O cell configuration for multiple I/O standards
GB2437568B (en) 2006-04-24 2009-02-11 Univ Sheffield Electrical machines

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6402853A (de) * 1964-03-18 1965-09-20
US3581107A (en) * 1968-03-20 1971-05-25 Signetics Corp Digital logic clamp for limiting power consumption of interface gate
DE1762118A1 (de) * 1968-04-11 1970-04-09 Telefunken Patent Spannungsdiskriminator zur UEberwachung beider Grenzwerte eines Spannungsbereiches
US3739200A (en) * 1971-09-27 1973-06-12 Agostino M D Fet interface circuit

Also Published As

Publication number Publication date
FR2328325B1 (de) 1979-08-17
JPS50149244A (de) 1975-11-29
DE2417054B2 (de) 1976-02-05
GB1503698A (en) 1978-03-15
US4032800A (en) 1977-06-28
CH585486A5 (de) 1977-02-28
DE2417054A1 (de) 1975-10-16
FR2328325A1 (fr) 1977-05-13
SE7503528L (sv) 1975-10-09
JPS5542782B2 (de) 1980-11-01
NL7501768A (nl) 1975-10-10
SE399349B (sv) 1978-02-06
DE2417054C3 (de) 1983-02-10
CA1027643A (en) 1978-03-07
ATA697674A (de) 1976-04-15
BE827555A (fr) 1975-07-31
IT1034869B (it) 1979-10-10

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Legal Events

Date Code Title Description
ELJ Ceased due to non-payment of the annual fee