AU3413493A - Method and device for tuning of an internal generated clock pulse signal - Google Patents

Method and device for tuning of an internal generated clock pulse signal

Info

Publication number
AU3413493A
AU3413493A AU34134/93A AU3413493A AU3413493A AU 3413493 A AU3413493 A AU 3413493A AU 34134/93 A AU34134/93 A AU 34134/93A AU 3413493 A AU3413493 A AU 3413493A AU 3413493 A AU3413493 A AU 3413493A
Authority
AU
Australia
Prior art keywords
tuning
pulse signal
clock pulse
generated clock
internal generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU34134/93A
Inventor
Jan-Olov Bergstrom
Lars Liljegren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB AB
Original Assignee
Asea Brown Boveri AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asea Brown Boveri AB filed Critical Asea Brown Boveri AB
Publication of AU3413493A publication Critical patent/AU3413493A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AU34134/93A 1992-01-20 1993-01-19 Method and device for tuning of an internal generated clock pulse signal Abandoned AU3413493A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9200137A SE502458C2 (en) 1992-01-20 1992-01-20 Method and apparatus for tuning internally generated clock pulse signal
SE9200137 1992-01-20

Publications (1)

Publication Number Publication Date
AU3413493A true AU3413493A (en) 1993-08-03

Family

ID=20385051

Family Applications (1)

Application Number Title Priority Date Filing Date
AU34134/93A Abandoned AU3413493A (en) 1992-01-20 1993-01-19 Method and device for tuning of an internal generated clock pulse signal

Country Status (3)

Country Link
AU (1) AU3413493A (en)
SE (1) SE502458C2 (en)
WO (1) WO1993014570A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726713B1 (en) * 1994-11-09 1997-01-24 Sgs Thomson Microelectronics CIRCUIT FOR DATA TRANSMISSION IN ASYNCHRONOUS MODE WITH FREQUENCY FREQUENCY OF RECEIVER SET ON THE TRANSMISSION FREQUENCY
NO307728B1 (en) * 1997-06-03 2000-05-15 Abb Research Ltd Steps to obtain time synchronization on a network
AU7758298A (en) * 1998-04-09 1999-11-01 Nokia Networks Oy Node control unit of an access node in a telecommunications network

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4131861A (en) * 1977-12-30 1978-12-26 International Business Machines Corporation Variable frequency oscillator system including two matched oscillators controlled by a phase locked loop
US4633193A (en) * 1985-12-02 1986-12-30 At&T Bell Laboratories Clock circuit synchronizer using a frequency synthesizer controlled by a frequency estimator
US4835481A (en) * 1986-09-30 1989-05-30 Siemens Aktiengesellschaft Circuit arrangement for generating a clock signal which is synchronous in respect of frequency to a reference frequency

Also Published As

Publication number Publication date
SE9200137L (en) 1993-07-21
SE502458C2 (en) 1995-10-23
SE9200137D0 (en) 1992-01-20
WO1993014570A1 (en) 1993-07-22

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