TWI313929B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI313929B
TWI313929B TW092128309A TW92128309A TWI313929B TW I313929 B TWI313929 B TW I313929B TW 092128309 A TW092128309 A TW 092128309A TW 92128309 A TW92128309 A TW 92128309A TW I313929 B TWI313929 B TW I313929B
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TW
Taiwan
Prior art keywords
die
cavity
substrate
conductive material
wall
Prior art date
Application number
TW092128309A
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Chinese (zh)
Other versions
TW200416989A (en
Inventor
A Gerber Mark
A Joiner Bennett
Antonio Montes De Oca Jose
A Thompson Trent
Original Assignee
Freescale Semiconductor Inc
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Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200416989A publication Critical patent/TW200416989A/en
Application granted granted Critical
Publication of TWI313929B publication Critical patent/TWI313929B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

1313929 玖、發明說明： 【發明所屬之技術領域】 本發明在美國已作為專利申請案第本申請案已在2〇〇2年 1月8日於美國提出，其專利中請案號為第·9g,959號。 本發明大體上係關於一種半導體裝置，更特定言之，係 關於一種具有改良熱消散之封裝半導體裝置。 【先前技術】 在封裝積體電路時，提供「允許使由於該積體電路晶粒 〈運行而產生的熱量得以消散」之封裝極為重要。為將熱 :移除，m常將一散熱器連接至該積體電路之表面以使熱 I和除1散熱器可為通常連接至該積體電路晶粒之底部 =非主動表面的該封裝之傳導部分H將散熱器添 口土孩晶粒底邵可增加該封裝之厚度。在—些應用中，例 如’在仃動電話中’要求較低側面之封裝以減小電話之尺 寸因此要求具有低側面且同時仍具有良好熱消散之封 裝的積體電路。 ' 【發明内容】 、大上’本發明提供一種具有改良之熱消散之低侧面半 導體裝置’其中將在—表面上具有主動電路系統之半道俨 晶粒安置於—封裝基板的空U。該封裝基板具有 表面及M d第—表面相對之第二表面。該空腔形成於該第 表面内並延伸人孩封裝基板。該空腔具有—大體上垂直 万；这第一及第—表面之空腔壁。該積體電路晶粒具有一第 -表面及-與該第—表面相對之第二表面。該晶粒之外壁 88386 1313929 或邊緣大體上垂直於該空腔之第一及第二表面。可使用膠 帶或其它臨時支架將該晶粒臨時固定。將傳導材料分散於 晶粒與空腔壁之間的空間中。該傳導材料將該'晶粒之外壁 熱耦合至該空腔壁。在一具體實施例中，當將臨時支架移 除時，即暴露出該晶粒之後侧。在另一具體實施例中，該 封裝基板空腔包括一散熱器，以在製造過程中，至少部份 充作支架之用。 藉由在晶粒與空腔壁之間嵌入傳導黏著劑，該封裝基板 即可充當散熱器，同時提供一低侧面封裝。 【實施方式】 圖1 _5包括對根據本發明第一具體實誨例形成的封裝裝置 之連續橫截面圖之說明。 圖1說明根據本發明之一具體實施例之半導體裝置10。半導 體裝置10包括一封裝基板12及一半導體晶粒20。該封裝基板 包括一具有複數個引線接頭焊墊14之頂面及一空腔22。基板 12之底面包括多個焊墊16。焊墊16具有傳導性且可用於各種 目的。例如，焊墊1 6可用來安裝分立的裝置，可用來接收用 於測試目的之測試探針，或可用來接收傳導互連（例如焊球） 。圖1亦說明了施用於基板12底部之臨時支架1 8。在該所說明 之具體實施例中，臨時支架1 8為在一側塗覆有黏著劑之膠帶 ，其將臨時支架U連接至該基板。在本發明之另一具體實斿 例中，基板12包含f導體，例如可用於將一個或多個晶粒互 連至外部接點（未圖示）之軌跡線及通路。此外，基板12可包 括多個内部金屬層（未圖示）。 88386 1313929 藉由將晶粒20之底面固定至臨時支架丨8，將晶粒2〇安置 於位於空腔22中心的臨時支架1 8之頂部。臨時支架丨8作為 支搏構件’以在隨後的製造步驟中將晶粒2 〇固定在空腔2 2 之内。應注意.可將晶粒連接材料施加於晶粒2 〇之底部， 但此在圖1中並未顯示。臨時支架丨8可延伸或可不延伸至基 板1 2之整個底面❶應注意：在該所說明的具體實施例中， 晶粒20之頂面延伸出空腔22 ’並高出基板12之表面。然而 ’在其它具體實施例中，晶粒20可完全位於空腔22之内。 圖2說明了將傳導材料24分散於空腔22之壁與晶粒2〇之 間的空間之後的半導體裝置10。在該說明之具體實施例中 ’傳導材料24為基於環氧樹脂之傳導性黏著劑。例如，傳 導材料24可為填充有銀之環氧樹脂。如圖2所說明，傳導材 料24完全填充空腔22，並視情況可覆蓋基板12之頂面。然 而，若僅大體上填充該空腔，即可獲得合理的熱效能。 圖3說明了在將引線接頭26連接在焊墊丨4與晶粒2〇上的 士T蟄（未圖示）之間後的半導體裝置1 〇。應注意，可在連接引 線接頭26之前或在下文所述的圖4之封裝步驟後將臨時支 架18移除。 圖4說明了封裝之後的半導體裝置1(^可藉由傳遞模塑法 、覆頂式分配法（glob top dispensing)或其它密封方法中的一 種來私用余封材料28。應注意：傳導材料24之導熱性應大 於密封材料28之導熱性， 圖5說明了連接至一印刷電路板（PCB) 3〇之半導體裝置1〇 。可以多種方式在半導體裝置10與PCB 3〇之間建立電連接 88386 1313929 圖5 δ尤明一種基板栅格陣列（iand grid array)，其使用絲網 印刷焊料（screen printed 3〇1(ΐ6Γ)36Η*ρ(：Β 3〇中的焊墊 W 連接至基板1 2上的焊墊丨6。使用絲網印刷焊料3 8以將晶粒 2曰〇之曝露的後側連接至焊墊34。熟悉此項技術者將瞭解： 晶粒=之後側將需要—可坪接表面來以此方式連接晶粒加 <曝路的後側。或者，若晶粒2〇之後側不具有可焊接表面 或在一特定應用中焊料之使用非吾人所樂見，則可使用導 熱展層填料或介面材料。在圖5之具體實施例中，在晶粒 、、吁中生成的热里將經由連接3 8及經由傳導材料2 4導出 。精由傳料料24擴散至封裝基板12之熱量將藉由連接36 傳導至PCB 3〇。經由傳導材料24傳導至基板12之埶量亦將 自該封裝積體電路裝置之頂部消散。將熱量經由傳導材料 I4擴散至封裝基板’可大幅提升僅藉由連接38之傳導而獲 仵的熱效说。在另—具體實施例中，連接Μ可略之，且 由傳導材料24將埶量 曰 里傳導至基板12及PCB 30，可實現改良 性、更簡易之印刷電路板總成、減低之成本及盥目 页可獲得之低側面封裝相比而言更低侧面之裝置。’、 置之連Ρ 2對根據本發明第二具體實施例形成的封裝裝 置t連、，檢截面圖之說明。 二！Λ根據本發明另-具體實施例之半導體裝置5。 Μ ^ Λ ^ .农基板52及一半導體晶粒60。該 土。—具有複數個引線接頭焊塾54之頂面及一空 底面包括多個洋塾56。焊塾56具有傳導性 万、目的。例如’焊心6可用來安裝分立的裝置 88386 1313929 w來接收用於測試目的之測試探針，或可用來接收傳 而互連(例如烊球)。圖6亦說明了具有延伸跨越空腔7〇之底 :積體晶粒連接焊#的基板52。在空腔壁之頂部邊緣形 '•綷料遮罩隆含58。在該說明之具體實施例中，自傳導 =料（例如銅）形成該積體晶粒連接焊墊。在本發明之一具體 :她例中，基板52包含電導體，例如可用於將—個或多個 卵粒互連至外邵接點（未圖示）之軌跡線及通路。此外，基板 52可包括多個内部金屬層（未圖示）。 藉由以ΘΕ(粒連接材料64將晶粒60之底面固定至積體晶粒 連接焊墊，將晶粒6〇安置於位於空腔7〇中心。積體電路晶 粒60具有一頂面（或主動表面）及一與該頂面相對之底面。該 晶粒之外壁或邊緣大體上垂直於該空腔之第一及第二表面 。在一具體實施例中，該積體電路晶粒之底面大體上與該 封裝基板之底面共面。晶粒60包括切入該主動表面之頂部 邊緣的突出部分62。在一具體實施例中，可在將晶圓鋸成 多個晶粒時形成突出部分62。自兩步驟鋸割加工獲得該突 出邵分62。在第一步驟中，使用一較寬锯條以製作一第一 、部分切口。在第二步驟中’使用一較窄鋸條自該第一部 分切口鋸割第二切口，完成將該晶圓分割成多個晶粒之程 序。應注意：在其它具體實施例中，可以其它方式形成該 突出部分62。 基板52包栝一沿空腔70週邊之焊料遮罩隆脊58。沈積該 焊料遮罩隆脊以防土所分配的傳導材料72覆蓋焊墊5 4。 圖7說明了在將傳導材料72分散於空腔70之壁與晶粒60 88386 -10- 1313929 <間的玉間 < 後的半導體裝置5〇。在該說明之具體實施例 中傳導材料72為基於環氧樹脂之傳導性黏著劑且將晶粒 '.彖或外壁傳導結合至空腔7 0之壁。例如，傳導材 料72可為填充有銀之環氧樹脂。如圖7所說明，傳導材料72 私工腔70填充至晶粒6〇上的突出部分62及基板上的焊料 逖罩隆含58。焊料遮罩隆脊58之功能為防止傳導材料意 外覆蓋引線接頭坪塾54。同樣地，冑出部分62之功能為防 止傳導材料72覆蓋晶粒6〇之主動表面。 圖8說明了在將引線接頭74連接於焊墊54與晶粒6〇上的 焊墊（未圖示）之間後的半導體裝置5〇。 圖9說明了密封之後的半導體裝置5〇。可以傳遞模塑法、 覆頂式刀配法（glob top dispensing)或其它密封方法中的一 種來施用密封材料78。應注意：傳導材料72之導熱性應大 於密封層之導熱性。 圖1〇3兄明了連接至一印刷電路板（PCB) 8〇之半導體裝置 。可以多種方式在半導體裝置5〇與pcB 8〇之間建立電連 接。圖戦明-基板柵格陣列，其使用絲網印刷烊料％以 將PCB 80中的焊墊82連接至基板52上的焊塾56。視情況， 將絲網印刷焊料88用於將基板52之底部連接至焊塾料。或 者’若基板52之底部不具有可焊接表面或在—特定應用中 焊料（使用非吾人所樂見，則可使用導熱底層㈣或介面 在圖10之具體實施例中 主要經由連接88及經由傳 在晶粒60運行期間生成的熱量 導材料72傳導出 亦可藉由積體 88386 -il · 1313929 晶粒焊墊將熱量傳遞至傳導材料π。藉由傳導材料72擴散 土封衣基板52之熱量將經由連接86傳導至pCB 8〇。經由傳 導材料72傳導至基板52之熱量亦將自封裝積體電路裝置之 頂邵消散。將熱量經由傳導材料72擴散至封裝基板，可大 幅提升僅藉由連接88傳導而獲得之熱效能。在另一具體實 施例中，連接88可略之，且將藉由傳導材料將熱量傳導 至基板52及PCB 80，可在具有改良之熱效能的較低側面裝 置中貫現更簡易的印刷電路板總成及降低之成本。 圖11說明意欲用於本發明第一及第二具體實施例之封裝 基板9〇之頂視圖。例如，基板9〇可替代在圖1-圖5中所說明 的县體實施例中的基板丨2,或在圖6_圖1〇所說明的具體實施 倒中的基板52。封裝基板9〇包括用於接收晶粒94之空腔91 9玄腔9 1疋壁可具有複數個電鍍切斷部分％。在一具體膏 裱例中，藉由沿界定空腔壁之線以間隔方式鑽孔而形成該 Φ鍍切斷部分92。其後，以傳導材料（例如鎳或銅）將該等孔 電鍍。在其它具體實施例中’可以其它導熱材料電鍍該等 孔。如圖所示，可將該空腔佈線，以保留一半的電鍍通路 、刀政於军腔中的傳導材料在晶粒與電鍍切斷部分之間形 成傳導連接。因為在電鍍通路與内部平面之間建立了一直 接金屬連接，基板9〇為基板9〇之傳導内部平面（未圖示）提供 增鈿之熱耦合。或者，可不使用通路而電鍍該等空腔壁以 提供相似之結果。 應汪意：可使用基板90内的軌跡線及通路（未圖示）以將基 板90各個部分選擇性地互連。 88386 1313929 應注意：晶粒連接材料可為任意種類的適宜之材料，例 如黏性膠帶或非固態黏著劑⑽如膠水、環氧樹脂）。晶粒20 ㈣可為任何類型之積體電路、半導體裝置或其它類型之 電氣主動基板。本發明之替代具體實施例可具有任何數量 的封裝於封裝裝置内之晶朽？ 夏Μ足阳釭20或60。例如，替代具體 例可在封裝裝置内封裝多於—個的晶粒。 ”她 在上这4明書中’參照特定具體實施例對本發明進行了 ::直然而’普通熟悉此項技術者將暸解，可不悻離以下 ^專㈣圍所提出的本發明之範圍對其進行各種修改。 例如’在所說明具體實施例之形成中，可使用一 晶粒連接程序、引均姐_g ^ ， 且< . 序引線接頭程序及膠帶黏著程序，其中每少 程序在此項技術中均為 '夕 τ 1為已知。並且，可以引線框 frame)替代該基板。因此， 非限制性音μ (將0說明看作說明性意義而 已，转心我’且本發明之範圍意欲包含所有該等修改。 已政特疋具體實施例描 題之解決。钬而m 處、其它優勢及多個問 m 以盈處、優勢、問題之解決及可導致 何並處、優勢或解決之發. 要素並非為兮 /、又侍更為顯者炙任何 或要素寺申請專利範圍之關鍵、必要或基本的特點 【圖式簡單說明】 二!:::明::明’且—，其中相 仃观表不同樣的元件，且其中： 圖1-5包括對根據本 之連續橫截面网、 $具"施例形成的封裝裝置 "仄饯面圖〈說明；及 圖6 -1 〇包括料士 括對根據本發明第二具體實施例形成的封裝裝 88386 -13 - 1313929 置之連續橫截面圖之說明。 圖11說明用於本發明第一及第二具體實施例之封裝基板 之頂視圖。 熟悉此項技術者將理解：為簡單清晰起見，並未按照比 例纟會製圖中的元件。例如，相對於其它元件而言，圖中的 某些元件之尺寸可誇大，以有助於改良對本發明各種具體 實施例之理解。 圖式代 表符 號說明】 10, 50 半導體裝置 12, 52, 90 封裝基板 14, 54 引線接頭焊墊 16, 34, 56 焊墊 18 臨時支架 20, 60 半導體晶粒 22, 70, 91 空腔 24, 72 傳導材料 26 引線接頭 28 密封材料 30, 80 印刷電路板 36, 38, 88 連接 62 突出部分 64 晶粒連接材料 86 焊料 92 電鍍 88386 -14-1313929 玖, invention description: [Technical field of invention] The invention has been filed in the United States as a patent application. The application was filed in the United States on January 8, 2002. 9g, 959. SUMMARY OF THE INVENTION The present invention generally relates to a semiconductor device, and more particularly to a packaged semiconductor device having improved heat dissipation. [Prior Art] When the integrated circuit is packaged, it is extremely important to provide a package that allows the heat generated by the operation of the integrated circuit die to be dissipated. To remove heat: m, a heat sink is often attached to the surface of the integrated circuit such that the heat I and the heat sink 1 can be the package that is typically connected to the bottom of the integrated circuit die = inactive surface. The conductive portion H adds the heat sink to the bottom of the die to increase the thickness of the package. In some applications, such as 'in a slapphone', a lower side package is required to reduce the size of the phone, thus requiring an integrated circuit having a low side and still having a good heat dissipation package. SUMMARY OF THE INVENTION The present invention provides a low-side semiconductor device having improved heat dissipation, wherein a half-turn dies having an active circuitry on the surface are disposed on the space U of the package substrate. The package substrate has a surface and a second surface opposite to the surface of the M d . The cavity is formed in the first surface and extends the human package substrate. The cavity has - substantially perpendicular; the cavity walls of the first and first surfaces. The integrated circuit die has a first surface and a second surface opposite the first surface. The outer wall 88386 1313929 or edge of the die is substantially perpendicular to the first and second surfaces of the cavity. The die can be temporarily secured using a tape or other temporary support. The conductive material is dispersed in the space between the die and the cavity wall. The conductive material thermally couples the outer wall of the 'die to the cavity wall. In a specific embodiment, when the temporary support is removed, the rear side of the die is exposed. In another embodiment, the package substrate cavity includes a heat sink for at least partially serving as a support during the manufacturing process. By embedding a conductive adhesive between the die and the cavity walls, the package substrate acts as a heat sink while providing a low profile package. [Embodiment] Figs. 1 to 5 include an explanation of a continuous cross-sectional view of a packaging device formed in accordance with a first embodiment of the present invention. 1 illustrates a semiconductor device 10 in accordance with an embodiment of the present invention. The semiconductor device 10 includes a package substrate 12 and a semiconductor die 20. The package substrate includes a top surface having a plurality of lead tab pads 14 and a cavity 22. The bottom surface of the substrate 12 includes a plurality of pads 16. Pad 16 is conductive and can be used for a variety of purposes. For example, pad 16 can be used to mount discrete devices that can be used to receive test probes for testing purposes or can be used to receive conductive interconnects (e.g., solder balls). Figure 1 also illustrates a temporary support 18 applied to the bottom of the substrate 12. In the illustrated embodiment, the temporary holder 18 is a tape coated with an adhesive on one side that connects the temporary holder U to the substrate. In another embodiment of the invention, substrate 12 includes an f-conductor, such as a trace line and via that can be used to interconnect one or more dies to external contacts (not shown). Additionally, substrate 12 can include a plurality of internal metal layers (not shown). 88386 1313929 The die 2 is placed on top of the temporary support 18 at the center of the cavity 22 by securing the bottom surface of the die 20 to the temporary support 丨8. The temporary holder 8 is used as a stroke member to secure the die 2 in the cavity 2 2 in a subsequent manufacturing step. It should be noted that the die attach material can be applied to the bottom of the die 2, but this is not shown in FIG. The temporary carrier 8 may or may not extend over the entire bottom surface of the substrate 12. It should be noted that in the illustrated embodiment, the top surface of the die 20 extends out of the cavity 22' and above the surface of the substrate 12. However, in other embodiments, the die 20 may be located entirely within the cavity 22. Figure 2 illustrates the semiconductor device 10 after dispersing the conductive material 24 in the space between the walls of the cavity 22 and the die 2〇. In the specific embodiment of the description, the conductive material 24 is an epoxy-based conductive adhesive. For example, the conductive material 24 can be an epoxy filled with silver. As illustrated in Figure 2, the conductive material 24 completely fills the cavity 22 and may cover the top surface of the substrate 12 as appropriate. However, reasonable thermal performance can be obtained if only the cavity is substantially filled. Fig. 3 illustrates the semiconductor device 1 after the lead tab 26 is connected between the pad 4 and the pad T (not shown) on the die 2. It should be noted that the temporary support 18 can be removed prior to the connection of the lead joint 26 or after the packaging step of Figure 4 described below. 4 illustrates that the semiconductor device 1 after packaging can be used for private use of the encapsulation material 28 by transfer molding, glob top dispensing or other sealing methods. It should be noted that the conductive material The thermal conductivity of 24 should be greater than the thermal conductivity of the sealing material 28. Figure 5 illustrates a semiconductor device 1 connected to a printed circuit board (PCB). Electrical connections can be made between the semiconductor device 10 and the PCB 3〇 in a variety of ways. 88386 1313929 Figure 5 δ 尤 明 An array of array grids (iand grid array) using screen printed solder (screen printed 3〇1 (ΐ6Γ) 36Η*ρ(: 焊 3〇 solder pad W connected to substrate 1 Pad 丨6 on 2. Use screen-printed solder 38 to connect the exposed back side of the die 2 to the pad 34. Those skilled in the art will understand that: the die = the back side will be needed - The splicing surface is used to connect the die plus the rear side of the exposure in this way. Alternatively, if the back side of the die 2 不 does not have a solderable surface or the use of solder in a particular application is not desired, Use thermally conductive build-up filler or interface material. Figure 5 In the embodiment, the heat generated in the die, the bump will be conducted via the connection 38 and via the conductive material 24. The heat diffused from the transfer material 24 to the package substrate 12 will be conducted to the PCB through the connection 36. The amount of conduction to the substrate 12 via the conductive material 24 will also be dissipated from the top of the packaged integrated circuit device. The diffusion of heat through the conductive material I4 to the package substrate can greatly enhance the conduction only by the conduction of the connection 38. In another embodiment, the connection can be omitted, and the conductive material 24 conducts the measurement to the substrate 12 and the PCB 30, thereby realizing a modified and simple printed circuit board assembly. The cost of the reduction and the lower side of the low side package available on the page can be compared to the device of the lower side package. 2, the connection device 2 is connected to the package device according to the second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A semiconductor device 5 according to another embodiment of the present invention. Μ ^ Λ ^. Agricultural substrate 52 and a semiconductor die 60. The soil has a top surface of a plurality of lead tabs 54 And an empty bottom surface including a plurality of artichokes 56 The solder fillet 56 is conductive and purpose. For example, the solder core 6 can be used to mount discrete devices 88386 1313929 w to receive test probes for testing purposes, or can be used to receive and interconnect (eg, croquet). 6 also illustrates a substrate 52 having a bottom that extends across the cavity 7: integrated die attach weld #. The top edge of the cavity wall is shaped as a '• 遮 遮 隆 58 58. In the specific embodiment of the description The self-conducting material (for example, copper) forms the integrated die bond pad. In one embodiment of the invention: in the example, the substrate 52 comprises an electrical conductor, for example, for interconnecting one or more eggs The trajectory and path to the external contact (not shown). Additionally, substrate 52 can include a plurality of internal metal layers (not shown). The die 6 is disposed at the center of the cavity 7 by fixing the bottom surface of the die 60 to the integrated die bond pad by a germanium (grain joining material 64). The integrated circuit die 60 has a top surface ( Or an active surface) and a bottom surface opposite the top surface. The outer wall or edge of the die is substantially perpendicular to the first and second surfaces of the cavity. In a specific embodiment, the integrated circuit die The bottom surface is substantially coplanar with the bottom surface of the package substrate. The die 60 includes a protruding portion 62 cut into the top edge of the active surface. In a specific embodiment, the protruding portion can be formed when the wafer is sawed into a plurality of crystal grains. 62. The protruding portion 62 is obtained from a two-step sawing process. In the first step, a wider blade is used to make a first, partial slit. In the second step, 'using a narrower blade from the first A portion of the slit saws the second slit to complete the process of dividing the wafer into a plurality of dies. It should be noted that in other embodiments, the protruding portion 62 may be formed in other manners. Surrounding solder mask ridge 58. Deposition The solder mask ridges cover the solder pads 54 from the conductive material 72 dispensed by the soil. Figure 7 illustrates the dispersion of the conductive material 72 between the walls of the cavity 70 and the grains 60 88386 -10- 1313929 < In the embodiment of the description, the conductive material 72 is an epoxy-based conductive adhesive and conductively bonds the die's or outer wall to the wall of the cavity 70. For example, the conductive material 72 can be an epoxy filled with silver. As illustrated in Figure 7, the conductive material 72 is filled with a recess 62 on the die 6 and a solder cap 58 on the substrate. The function of the solder mask ridge 58 is to prevent the conductive material from accidentally covering the lead joint pad 54. Similarly, the scooping portion 62 functions to prevent the conductive material 72 from covering the active surface of the die 6. Figure 8 illustrates the lead The terminal 74 is connected to the semiconductor device 5A between the pad 54 and a pad (not shown) on the die 6. The semiconductor device 5A after sealing is illustrated in Fig. 9. The molding method can be transferred and the top can be covered. One of the glob top dispensing or other sealing methods The sealing material 78 is applied. It should be noted that the thermal conductivity of the conductive material 72 should be greater than the thermal conductivity of the sealing layer. Figure 1-3 shows a semiconductor device connected to a printed circuit board (PCB) 8 。. The semiconductor device 5 can be used in various ways. An electrical connection is established between the 〇 and the pcB 8 。. The substrate-substrate grid array uses screen printing %% to connect the pads 82 in the PCB 80 to the pads 56 on the substrate 52. As appropriate, Screen-printed solder 88 is used to connect the bottom of substrate 52 to the solder paste. Or 'If the bottom of substrate 52 does not have a solderable surface or solder in a particular application (use is not something that is good for us, heat can be used) The bottom layer (4) or interface is conducted in a particular embodiment of FIG. 10 primarily via connection 88 and via heat conductive material 72 generated during operation of die 60, or may be heatd by a paddle 88386-il 1313929 die pad Passed to the conductive material π. The heat diffused by the conductive material 72 to the earth containment substrate 52 will be conducted via connection 86 to pCB 8〇. The heat conducted to the substrate 52 via the conductive material 72 will also dissipate from the top of the packaged integrated circuit device. The diffusion of heat through the conductive material 72 to the package substrate greatly enhances the thermal performance obtained by conduction only through the connection 88. In another embodiment, the connection 88 can be omitted and the heat will be conducted to the substrate 52 and the PCB 80 by the conductive material, allowing for a simpler printed circuit board in a lower side device with improved thermal performance. Assembly and reduced costs. Figure 11 illustrates a top view of a package substrate 9 that is intended for use in the first and second embodiments of the present invention. For example, the substrate 9A may be substituted for the substrate 丨2 in the embodiment of the county body illustrated in Figs. 1 to 5, or the substrate 52 inverted in the embodiment illustrated in Fig. 6 to Fig. 1 . The package substrate 9A includes a cavity for receiving the die 94. 9 9 The cavity 9 1 The wall may have a plurality of plated cut portions %. In a specific paste example, the Φ plated cut portion 92 is formed by drilling holes in a space along a line defining a cavity wall. Thereafter, the holes are plated with a conductive material such as nickel or copper. In other embodiments, the holes may be plated with other thermally conductive materials. As shown, the cavity can be routed to maintain a conductive connection between the die and the plated cut portion by retaining half of the plating path and the conductive material in the cavity. Since a permanent metal connection is established between the plated via and the inner plane, the substrate 9 turns into a thermally conductive internal plane (not shown) that provides enhanced thermal coupling. Alternatively, the cavity walls can be plated without the use of vias to provide similar results. Wang Yi: Track lines and vias (not shown) within the substrate 90 can be used to selectively interconnect portions of the substrate 90. 88386 1313929 It should be noted that the die attach material may be any suitable material, such as a viscous tape or a non-solid adhesive (10) such as glue or epoxy. The die 20 (d) can be any type of integrated circuit, semiconductor device or other type of electrically active substrate. Alternative embodiments of the present invention can have any number of crystals encapsulated in a packaged device? Xia Wei, Yang Yang, 20 or 60. For example, instead of a specific example, more than one die can be packaged within the package. The invention has been described with reference to a particular embodiment of the invention in the following description:: However, those skilled in the art will understand that the scope of the invention as set forth in the following paragraphs (4) Various modifications are made. For example, 'in the formation of the specific embodiment, a die connection procedure, a sigma _g ^ , and a sequence lead joint procedure and a tape bonding procedure can be used, wherein each less program is here. In the technique, it is known that ̄τ 1 is known, and the substrate can be replaced by a lead frame. Therefore, the non-limiting tone μ (the description of 0 is regarded as an illustrative meaning, and the heart is me' and the present invention The scope is intended to cover all such modifications. The specific features of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations of the stipulations. The solution is not the key, necessary or basic features of the patent scope of any or elemental temple. The elements are not for the 兮/, but also for the singularity. [Simplified illustration] Two!::: Ming:: Ming' and - , which is not the same as the watch And wherein: Figures 1-5 include a packaged device according to the present continuous cross-section network, a "applied"example; and Figure 6-1 includes a pair of materials DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE PREPARED EMBODIMENT 88386 - 13 - 1313929 FORMED IN THE SECOND EMBODIMENT OF THE INVENTION Figure 11 illustrates a top view of a package substrate for use in the first and second embodiments of the present invention. The skilled artisan will understand that the elements in the drawings are not drawn to scale for the sake of simplicity and clarity. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve various aspects of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) DESCRIPTION OF SYMBOLS 10, 50 Semiconductor device 12, 52, 90 Package substrate 14, 54 Lead tabs 16, 34, 56 Pad 18 Temporary bracket 20, 60 Semiconductor die 22, 70 , 91 Cavity 24, 72 Conductive material 26 Lead connector 28 Sealing material 30, 80 Printed circuit board 36, 38, 88 Connection 62 Projection 64 Die joining material 86 Solder 92 Plating 88386 -14-

Claims (1)

I313f2^128309號專利申請案 fa 中文申請專利範圍替換本(95年10月） 拾、申請專利範圍： 1. 一種半導體裝置，其包含： 一封裝基板，其具有一第一表面及一與該第一表面相 對之第二表面、及一形成於該第一表面内並延伸入該封 裝基板之空腔，該空腔具有一大體上垂直於該第一及第 二表面之空腔壁； 一積體電路晶粒，其中該積體電路晶粒之至少一部分 位於該空腔内，且其中該積體電路晶粒具有一第一表面 ，一與該第一表面相對之第二表面，一大體上垂直於該 第一及第二表面之外壁及在該積體電路晶粒之該第一 表面及該外壁之一交又處之一突出部分，其中該外壁之 至少一部分大體上面向該空腔壁；及 一位於該空腔中之傳導材料，其中該傳導材料將該積 體電路晶粒之該外壁熱耦合至該空腔壁。 88386-950929.docI313f2^128309 Patent Application fa Chinese Patent Application Renewal (October 95) Pickup, Patent Application Range: 1. A semiconductor device comprising: a package substrate having a first surface and a first a surface opposite the second surface, and a cavity formed in the first surface and extending into the package substrate, the cavity having a cavity wall substantially perpendicular to the first and second surfaces; a body circuit die, wherein at least a portion of the integrated circuit die is located in the cavity, and wherein the integrated circuit die has a first surface, a second surface opposite the first surface, a substantially a protruding portion perpendicular to the outer wall of the first and second surfaces and at the intersection of the first surface and the outer wall of the integrated circuit die, wherein at least a portion of the outer wall substantially faces the cavity wall And a conductive material in the cavity, wherein the conductive material thermally couples the outer wall of the integrated circuit die to the cavity wall. 88386-950929.doc
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TW200416989A (en) 2004-09-01

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